A robust, subthreshold 12T SRAM bitcell with BL leakage compensation and bit-interleaving capability. - Debin Kong; Jia Yuan; Shan-Shan Li; Heng You; Shushan Qiao (IEICE Electron. Express, 2018)

Design of low-power low-area asynchronous iterative multiplier. - Heng You; Yong Hei; Jia Yuan; Weidi Tang; Xu Bai; Shushan Qiao (IEICE Electron. Express, 2019)

An ultra-low leakage energy efficient level shifter with wide conversion range. - Heng You; Jia Yuan; Weidi Tang; Yi Yu; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

A design method of CPR for wide voltage design. - Yi Yu; Zhi-jiu Zhu; Heng You; Jia Yuan; Shushan Qiao; Yong Hei (IEICE Electron. Express, 2019)

A 8bits, 6.2ps resolution two-step time-to-digital converter with set-reset-based arbiters and signal tracking mechanism. - Yong-sen Wang; Song Cheng; A.-long Zhao; Heng You; Shushan Qiao (IEICE Electron. Express, 2020)

A fast and low-power level shifter for multi-supply voltage designs. - Jialu Yin; Jia Yuan; Heng You; Peng Wang 204; Shushan Qiao (IEICE Electron. Express, 2020)

An Energy-Efficient Level Shifter for Ultra Low-Voltage Digital LSIs. - Heng You; Jia Yuan; Weidi Tang; Shushan Qiao; Yong Hei (IEEE Trans. Circuits Syst., 2020)

A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (ISCAS, 2021)

A 8.83nW, 0.14ppm/℃ crystal oscillator using duty-cycling automatic amplitude control. - Yulian Wang; Xiaoyu Hu; Xinxin Ren; Heng You; Dashan Shi; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2021)

Area-energy efficient CORDICs using new elementary-angle-set and base-2 exponent expansions scheme. - Yong-sen Wang; Yu-qun Xue; Heng You; Shushan Qiao (IEICE Electron. Express, 2021)

Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Cross-domain adaptive transfer reinforcement learning based on state-action correspondence. - Heng You; Tianpei Yang; Yan Zheng 002; Jianye Hao; Matthew E. Taylor (UAI, 2022)

A 0.6V 1.76nW power on reset circuit with high accuracy. - Yulian Wang; Xiaoyu Hu; Xinxin Ren; Dashan Shi; Heng You; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2022)

A fully integrated GaAs HBT power amplifier with enhanced efficiency for 5-GHz WLAN applications. - Haohan Yang; Heng You; Shushan Qiao (IEICE Electron. Express, 2022)

An Accurate Low-Power Power-on-Reset Circuit in 55-nm CMOS Technology. - Heng You; Jia Yuan; Zenghui Yu; Shushan Qiao (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low-Power High-Speed Sensing Scheme for Single-Ended SRAM. - Dashan Shi; Heng You; Jia Yuan; Yulian Wang; Shushan Qiao (IEICE Trans. Electron., 2022)

Transfer Learning based Agent for Automated Negotiation. - Siqi Chen 001; Qisong Sun; Heng You; Tianpei Yang; Jianye Hao (AAMAS, 2023)

Transfer Reinforcement Learning Based Negotiating Agent Framework. - Siqi Chen 001; Tianpei Yang; Heng You; Jianing Zhao; Jianye Hao; Gerhard Weiss 001 (PAKDD (2), 2023)

A Transfer Approach Using Graph Neural Networks in Deep Reinforcement Learning. - Tianpei Yang; Heng You; Jianye Hao; Yan Zheng 002; Matthew E. Taylor (AAAI, 2024)

A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications. - Heng You; Dashan Shi; Delong Shang; Yumei Zhou; Shushan Qiao (ISCAS, 2024)

A Dual-Wordline 6T SRAM Computing-In-Memory Macro Featuring Full Signed Multi-Bit Computation for Lightweight Networks. - Zupei Gu; Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Access, 2024)

A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks. - Heng You; Weijun Li; Delong Shang; Yumei Zhou; Shushan Qiao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Dynamic Decision Correction Framework Integrating Path Optimization and Incomplete Information Handling. - Ziye Zhou; Yanbin Guo; Xin Tang; Kehan Li; Heng You (GAIIS, 2025)

An energy-efficient readout method based on weight-flip-store coding and quantization cycle skipping technology for computing in memory. - Shukao Dou; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEICE Electron. Express, 2025)

A Charge Domain SRAM Computing-in-Memory Macro With Quantized Interval-Optimized ADC and Input Bit-Level Sparsity-Optimized P2O-DAC for 8-b MAC Operation. - Shukao Dou; Zupei Gu; Heng You; Yi Zhan; Shushan Qiao; Yumei Zhou (IEEE Trans. Very Large Scale Integr. Syst., 2025)