Delta-Sigma D/A Converter Using Binary- Weighted Digital-to-Analog Differentiator for Second-Order Mismatch Shaping. - Heng-Yu Jian; Zhiwei Xu 003; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c TRX. - David Murphy; Qun Jane Gu; Yi-Cheng Wu; Heng-Yu Jian; Zhiwei Xu 003; Adrian Tang 002; Frank Wang; Yu-Ling Lin; Ho-Hsian Chen; Chewnpu Jou; Mau-Chung Frank Chang (ESSCIRC, 2010)

A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator. - Heng-Yu Jian; Zhiwei Xu 003; Yi-Cheng Wu; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2010)

A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver. - David Murphy; Qun Jane Gu; Yi-Cheng Wu; Heng-Yu Jian; Zhiwei Xu 003; Adrian Tang 002; Frank Wang; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2011)

CMOS Prescaler(s) With Maximum 208-GHz Dividing Speed and 37-GHz Time-Interleaved Dual-Injection Locking Range. - Qun Jane Gu; Heng-Yu Jian; Zhiwei Xu 003; Yi-Cheng Wu; Mau-Chung Frank Chang; Yves Baeyens; Young-Kai Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2011)