A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

Resistance switching for RRAM applications. - Frederick T. Chen; Heng-Yuan Lee; Yu-Sheng Chen; Yenya Hsu; Lijie Zhang; Pang-Shiu Chen; Weisu Chen; Peiyi Gu; Wenhsing Liu; Sumin Wang; Chen-Han Tsai; Shyh-Shyuan Sheu; et al. (Sci. China Inf. Sci., 2011)

Fast-Write Resistive RAM (RRAM) for Embedded Applications. - Shyh-Shyuan Sheu; Kuo-Hsing Cheng; Meng-Fan Chang; Pei-Chia Chiang; Wen-Pin Lin; Heng-Yuan Lee; Pang-Shiu Chen; Yu-Sheng Chen; Frederick T. Chen; Ming-Jinn Tsai (IEEE Des. Test Comput., 2011)

Metal-Oxide RRAM. - H.-S. Philip Wong; Heng-Yuan Lee; Shimeng Yu; Yu-Sheng Chen; Yi Wu 016; Pang-Shiu Chen; Byoungil Lee; Frederick T. Chen; Ming-Jinn Tsai (Proc. IEEE, 2012)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

A nonvolatile look-up table using ReRAM for reconfigurable logic. - Wen-Pin Lin; Shyh-Shyuan Sheu; Chia-Chen Kuo; Pei-Ling Tseng; Meng-Fan Chang; Keng-Li Su; Chih-Sheng Lin; Kan-Hsueh Tsai; Sih-Han Lee; Szu-Chieh Liu; Yu-Sheng Chen; Heng-Yuan Lee; et al. (A-SSCC, 2014)

Data retention statistics and modelling in HfO2 resistive switching memories. - Stefano Ambrogio; Simone Balatti; Zhongqiang Wang; Yu-Sheng Chen; Heng-Yuan Lee; Frederick T. Chen; Daniele Ielmini (IRPS, 2015)

17.5 A 3T1R nonvolatile TCAM using MLC ReRAM with Sub-1ns search time. - Meng-Fan Chang; Chien-Chen Lin; Albert Lee; Chia-Chen Kuo; Geng-Hau Yang; Hsiang-Jen Tsai; Tien-Fu Chen; Shyh-Shyuan Sheu; Pei-Ling Tseng; Heng-Yuan Lee; Tzu-Kun Ku (ISSCC, 2015)

Analyzing inference robustness of RRAM synaptic array in low-precision neural network. - Rui Liu 005; Heng-Yuan Lee; Shimeng Yu (ESSDERC, 2017)

Highly Reliable Two-Step Charge-Pump Read Scheme for 1.5 F2/Bit Nonlinear Sub-Teraohm 0TNR Vertical ReRAM. - Tsai-Kan Chien; Lih-Yih Chiou; Chi-Shian Chang; Jing-Yu Huang; Chung-Han Wu; Heng-Yuan Lee; Shyh-Shyuan Sheu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. - Xin Si; He Qian; Meng-Fan Chang; Cheng-Xin Xue; Jian-Wei Su; Zhixiao Zhang; Sih-Han Li; Shyh-Shyuan Sheu; Heng-Yuan Lee; Ping-Cheng Chen; Huaqiang Wu (ASICON, 2019)

NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. - Chih-Cheng Chang; Ming-Hung Wu; Jia-Wei Lin; Chun-Hsien Li; Vivek Parmar; Heng-Yuan Lee; Jeng-Hua Wei; Shyh-Shyuan Sheu; Manan Suri; Tian-Sheuan Chang; Tuo-Hung Hou (DAC, 2019)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)