An 8-Bit 2.1-mW 350-MS/s SAR ADC With 1.5 b/cycle Redundancy in 65-nm CMOS. - Dengquan Li; Maliang Liu; Lei Zhao; Henghui Mao; Ruixue Ding; Zhangming Zhu (IEEE Trans. Circuits Syst., 2020)

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS. - Lei Zhao; Dengquan Li; Henghui Mao; Ruixue Ding; Zhangming Zhu (J. Circuits Syst. Comput., 2021)

A configurable nonbinary 7/8-bit 800-400 MS/s SAR ADC in 65 nm CMOS. - Henghui Mao; Dengquan Li; Shubin Liu (Microelectron. J., 2022)