Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation. - Valeriy Sukharev; Ara Markosian; Armen Kteyan; Levon Manukyan; Nikolay Khachatryan; Jun-Ho Choy; Hasmik Lazaryan; Henrik Hovsepyan; Seiji Onoue; Takuo Kikuchi; Tetsuya Kamigaki (ISQED, 2009)

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance. - Valeriy Sukharev; Armen Kteyan; Jun-Ho Choy; Henrik Hovsepyan; Ara Markosian; Ehrenfried Zschech; Rene Huebner (J. Electron. Test., 2012)

Post placement leakage reduction with stress-enhanced filler cells. - Jun-Ho Choy; Valeriy Sukharev; Armen Kteyan; Henrik Hovsepyan; Ramnath Venkatraman; Ruggero Castagnetti (ISLPED, 2015)

Assesment of CPI Stress Impact on IC Reliability and Performance in 2.5D/3D Packages. - Armen Kteyan; Henrik Hovsepyan; Jun-Ho Choy; Valeriy Sukharev (IRPS, 2019)