Henrique C. Freitas

According to our database1, Henrique C. Freitas authored at least 23 papers between 2006 and 2019.

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Timeline

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Bibliography

2019
A Fast Parallel K-Modes Algorithm for Clustering Nucleotide Sequences to Predict Translation Initiation Sites.
Journal of Computational Biology, 2019

A comprehensive performance evaluation of the BinLPT workload-aware loop scheduler.
Concurrency and Computation: Practice and Experience, 2019

2018
Energy Efficient Parallel K-Means Clustering for an Intel® Hybrid Multi-Chip Package.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Design Space Exploration of Energy Efficient NoC-and Cache-Based Many-Core Architecture.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
Scalable spatio-temporal parallel parameterizable stream-based JPEG-LS encoder.
IEICE Electronic Express, 2017

CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors.
Concurrency and Computation: Practice and Experience, 2017

Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation.
Concurrency and Computation: Practice and Experience, 2017

Energy Consumption Improvement of Shared-Cache Multicore Clusters Based on Explicit Simultaneous Multithreading.
Proceedings of the 2017 International Symposium on Computer Architecture and High Performance Computing Workshops, 2017

Assessing the Performance of the SRR Loop Scheduler with Irregular Workloads.
Proceedings of the International Conference on Computational Science, 2017

2016
Parallelization of the next Closure algorithm for generating the minimum set of implication rules.
Artif. Intell. Research, 2016

A Low-Cost Energy-Efficient Raspberry Pi Cluster for Data Mining Algorithms.
Proceedings of the Euro-Par 2016: Parallel Processing Workshops, 2016

2015
On the energy efficiency and performance of irregular application executions on multicore, NUMA and manycore platforms.
J. Parallel Distributed Comput., 2015

Performance evaluation of single- and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks.
J. Braz. Comp. Soc., 2015

2012
Parallel and distributed kmeans to identify the translation initiation site of proteins.
Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, 2012

2011
High Latency and Contention on Shared L2-Cache for Many-Core Architectures.
Parallel Processing Letters, 2011

Boosting Parallel Applications Performance on Applying DIM Technique in a Multiprocessing Environment.
Int. J. Reconfig. Comp., 2011

2010
A Distributed Algorithm for Formal Concepts Processing based on Search Subspaces.
Proceedings of the ICEIS 2010 - Proceedings of the 12th International Conference on Enterprise Information Systems, Volume 1, DISI, Funchal, Madeira, Portugal, June 8, 2010

2009
Performance Evaluation of NoC Architectures for Parallel Workloads.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Design of Interleaved Multithreading for Network Processors on Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
NOC architecture design for multi-cluster chips.
Proceedings of the FPL 2008, 2008

A High-Throughput Multi-cluster NoC Architecture.
Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

2007
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Reconfigurable crossbar switch architecture for network processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006


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