Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies. - Henrique Kessler; Plinio Finkenauer; Thiago H. Both; Leomar Soares da Rosa Jr.; Vinícius V. Camargo (ISCAS, 2020)

Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks. - Plinio Finkenauer; Henrique Kessler; Rafael Iankowski Soares; Vinícius V. Camargo (ISCAS, 2021)

Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions. - Henrique Kessler; Marcelo Schiavon Porto; Leomar Soares da Rosa Jr.; Vinícius V. Camargo (ISCAS, 2022)

Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. - Henrique Kessler; Murilo Bohlke; Leomar S. da Rosa; Marcelo Schiavon Porto; Vinícius V. Camargo (LASCAS, 2022)

Transistor Reordering for Electrical Improvement in CMOS Complex Gates. - Marcello M. Muñoz; Henrique Kessler; Marcelo Schiavon Porto; Vinícius V. Camargo (SBCCI, 2022)

Transistor-Level Radiation Hardening by Design Techniques in Complex Gates. - Bruno T. Ferraz; Henrique Kessler; Vinicius V. A. Camargo (J. Circuits Syst. Comput., 2022)