A hardware acceleration of a phylogenetic tree reconstruction with maximum parsimony algorithm using FPGA. - Henry Block; Tsutomu Maruyama (FPT, 2013)

An FPGA hardware acceleration of the indirect calculation of tree lengths method for phylogenetic tree reconstruction. - Henry Block; Tsutomu Maruyama (FPL, 2014)

An FPGA implementation of a phylogenetic tree reconstruction algorithm using an alternative second-pass optimization. - Henry Block; Tsutomu Maruyama (FPL, 2015)

An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization. - Henry Block; Tsutomu Maruyama (FPL, 2017)

FPGA Hardware Acceleration of a Phylogenetic Tree Reconstruction with Maximum Parsimony Algorithm. - Henry Block; Tsutomu Maruyama (IEICE Trans. Inf. Syst., 2017)