Predictive design space exploration using genetically programmed response surfaces. - Henry Cook; Kevin Skadron (DAC, 2008)

RAMP gold: an FPGA-based architecture simulator for multiprocessors. - Zhangxi Tan; Andrew Waterman; Rimas Avizienis; Yunsup Lee; Henry Cook; David A. Patterson 001; Krste Asanovic (DAC, 2010)

A case for FAME: FPGA architecture model execution. - Zhangxi Tan; Andrew Waterman; Henry Cook; Sarah Bird; Krste Asanovic; David A. Patterson 001 (ISCA, 2010)

Fast speaker diarization using a high-level scripting language. - Ekaterina Gonina; Gerald Friedland; Henry Cook; Kurt Keutzer (ASRU, 2011)

CUDA-level Performance with Python-level Productivity for Gaussian Mixture Model Applications. - Henry Cook; Ekaterina Gonina; Shoaib Kamil 001; Gerald Friedland; David A. Patterson 001; Armando Fox (HotPar, 2011)

CudaDMA: optimizing GPU memory bandwidth via warp specialization. - Michael Bauer 001; Henry Cook; Brucek Khailany (SC, 2011)

Portable parallel performance from sequential, productive, embedded domain-specific languages. - Shoaib Kamil 001; Derrick Coetzee; Scott Beamer; Henry Cook; Ekaterina Gonina; Jonathan Harper; Jeffrey Morlan; Armando Fox (PPoPP, 2012)

The RISC-V instruction set. - Andrew Waterman; Yunsup Lee; Rimas Avizienis; Henry Cook; David A. Patterson 001; Krste Asanovic (Hot Chips Symposium, 2013)

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. - Henry Cook; Miquel Moretó; Sarah Bird; Khanh Dao; David A. Patterson 001; Krste Asanovic (ISCA, 2013)

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators. - Yunsup Lee; Andrew Waterman; Rimas Avizienis; Henry Cook; Chen Sun 003; Vladimir Stojanovic; Krste Asanovic (ESSCIRC, 2014)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

Single-chip microprocessor that communicates directly using light. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael Georgas; Andrew Waterman; Jeffrey M. Shainline; Rimas Avizienis; Sen Lin 002; Benjamin Moss; Rajesh Kumar; et al. (Nat., 2015)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

Productive Design of Extensible On-Chip Memory Hierarchies. - Henry Cook (2016)

Microprocessor chip with photonic I/O. - Chen Sun 003; Mark T. Wade; Yunsup Lee; Jason S. Orcutt; Luca Alloatti; Michael S. Georgas; Andrew S. Waterman; Jeffrey M. Shainline; Rimas R. Avizienis; Sen Lin 002; Benjamin R. Moss; Rajesh Kumar; et al. (OFC, 2017)

Insights gained from constructing a large scale dynamic analysis platform. - Cody Miller; Dae Glendowne; Henry Cook; Thomas DeMarcus; Chris Lanclos; Patrick Pape (Digit. Investig., 2017)