DI-MMAP: A High Performance Memory-Map Runtime for Data-Intensive Applications. - Brian Van Essen; Henry Hsieh; Sasha Ames; Maya B. Gokhale (SC Companion, 2012)

A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. - Ming-Zhang Kuo; Henry Hsieh; Sang H. Dhong; Ping-Lin Yang; Cheng-Chung Lin; Ryan Tseng; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2014)

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. - Henry Hsieh; Sang H. Dhong; Cheng-Chung Lin; Ming-Zhang Kuo; Kuo-Feng Tseng; Ping-Lin Yang; Kevin Huang 005; Min-Jer Wang; Wei Hwang (CICC, 2015)

DI-MMAP - a scalable memory-map runtime for out-of-core data-intensive applications. - Brian Van Essen; Henry Hsieh; Sasha Ames; Roger A. Pearce; Maya B. Gokhale (Clust. Comput., 2015)

A 7nm 5G Mobile SoC Featuring a 3.0GHz Tri-Gear Application Processor Subsystem. - HsinChen Chen; Rolf Lagerquist; Ashish Nayak; Hugh Mair; Gokulakrishnan Manoharan; Ericbill Wang; Gordon Gammie; Efron Ho; Anand Rajagopalan; Lee-Kee Yong; Ramu Madhavaram; Madhur Jagota; et al. (ISSCC, 2021)