Analysis of STT-RAM cell design with multiple MTJs per access. - Henry Park; Richard Dorrance; Amr Amin Hafez; Fengbo Ren; Dejan Markovic; Chih-Kong Ken Yang (NANOARCH, 2011)

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs). - Fengbo Ren; Henry Park; Richard Dorrance; Yuta Toriyama; Chih-Kong Ken Yang; Dejan Markovic (ISQED, 2012)

Nearly Exact Analytical Formulation of the DNL Yield of the Digital-to-Analog Converter. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A digitally-calibrated 10GS/s reconfigurable flash ADC in 65-nm CMOS. - Ramy Yousry; Henry Park; E-Hung Chen; Chih-Kong Ken Yang (ISCAS, 2013)

In Situ SRAM Static Stability Estimation in 65-nm CMOS. - Henry Park; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

An INL Yield Model of the Digital-to-Analog Converter. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs. - Fengbo Ren; Henry Park; Chih-Kong Ken Yang; Dejan Markovic (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Stability Estimation of a 6T-SRAM Cell Using a Nonlinear Regression. - Henry Park; Chih-Kong Ken Yang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. - Bharath Raghavan; Aida Varzaghani; Lakshmi P. Rao; Henry Park; Xiaochen Yang; Zhi Huang; Yu Chen; Rama Kattamuri; Chunhui Wu; Bo Zhang 029; Jun Cao 001; Afshin Momtaz; et al. (VLSI Circuits, 2016)

A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS. - Namik Kocaman; Tamer A. Ali 001; Lakshmi P. Rao; Ullas Singh; Mohammed M. Abdul-Latif; Yang Liu; Amr Amin Hafez; Henry Park; Anand Vasani; Zhi Huang; Arvindh Iyer; Bo Zhang 029; et al. (IEEE J. Solid State Circuits, 2016)

A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. - Tamer A. Ali 001; Ramy Yousry; Henry Park; Ehung Chen; Po-Shuan Weng; Yi-Chieh Huang; Chun-Cheng Liu; Chien-Hua Wu; Shih-Hao Huang; Chungshi Lin; Ke-Chung Wu; Kun-Hung Tsai; et al. (ISSCC, 2019)

Male Adolescents' and Young Adults' Evaluations of Interracial Exclusion in Offline and Online Settings. - Henry Park; Seçil Gönültas; Kelly Lynn Mulvey; Melanie Killen; Martin D. Ruck (Cyberpsychology Behav. Soc. Netw., 2019)

6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. - Tamer A. Ali 001; Ehung Chen; Henry Park; Ramy Yousry; Yu-Ming Ying; Mohammed Abdullatif; Miguel Gandara; Chun-Cheng Liu; Po-Shuan Weng; Huan-Sheng Chen; Mohammad Elbadry; Qaiser Nehal; et al. (ISSCC, 2020)

56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology. - Tamer A. Ali 001; Mohammed Abdullatif; Henry Park; Ehung Chen; Ramy Awad; Miguel Gandara (CICC, 2021)

A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. - Henry Park; Mohammed Abdullatif; Ehung Chen; Ahmed Elmallah; Qaiser Nehal; Miguel Gandara; Tsz-Bin Liu; Amr Khashaba; Joonyeong Lee; Chih-Yi Kuan; Dhinessh Ramachandran; Ruey-Bo Sun; et al. (ISSCC, 2023)

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. - Ehung Chen; Henry Park; Mohammed Abdullatif; Miguel Gandara; Ahmed ElShater; Amr Khashaba; Shih-Hao Huang; Tsz-Bin Liu; Atharav Atharav; Joonyeong Lee; Qaiser Nehal; Mohamed Megahed; et al. (ISSCC, 2025)

7.4 A 112Gb/s DSP-Based PAM-4 Receiver with an LC-Resonator-Based CTLE for >52dB Loss Compensation in 4nm FinFET. - Henry Park; Qaiser Nehal; Miguel Gandara; Atharav Atharav; Joonyeong Lee; Jengfeng Li; Tamer Ali (ISSCC, 2025)