A balanced multilevel decomposition method. - Henry Selvaraj; Tadeusz Luba (ED&TC, 1995)

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis. - Tadeusz Luba; Henry Selvaraj (VLSI Design, 1995)

A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool. - Henry Selvaraj; Muthukumar Venkatesan (EUROMICRO, 1998)

Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. - Henry Selvaraj; Miroslawa Nowicka; Tadeusz Luba (VLSI Design, 1998)

Content based image retrieval using a neuro-fuzzy technique. - S. Kulkami; Brijesh K. Verma; P. Sharma; Henry Selvaraj (IJCNN, 1999)

A Parameter to Measure the Efficiency of FPGA Based Logic Synthesis Tools. - Henry Selvaraj; B. Li (EUROMICRO, 2000)

An Improved Column Compatibility Approach for Partition Based Functional Decomposition. - Muthukumar Venkatesan; Robert J. Bignall; Henry Selvaraj (EUROMICRO, 2000)

Decomposition of Boolean Relations and Functions in Logic Synthesis and Data Analysis. - Piotr Sapiecha; Henry Selvaraj; Michal Pleban (Rough Sets and Current Trends in Computing, 2000)

An Input-Output Encoding Approach for Serial Decomposition. - Venkatesan Muthukumar; Robert J. Bignall; Henry Selvaraj (SBCCI, 2000)

A variable partition approach for disjoint decomposition. - Muthukumar Venkatesan; Robert J. Bignall; Henry Selvaraj (ISCAS (5), 2001)

Functional Decomposition and Its Applications in Machine Learning and Neural Networks. - Henry Selvaraj; Piotr Sapiecha; Tadeusz Luba (Int. J. Comput. Intell. Appl., 2001)

FSM Implementation in Embedded Memory Blocks of Programmable Logic Devices Using Functional Decomposition. - Henry Selvaraj; Mariusz Rawski; Tadeusz Luba (ITCC, 2002)

Performance Driven Circuit Clustering and Partitioning. - Ling Wang 004; Henry Selvaraj (ITCC, 2002)

NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables. - Michal Pleban; Hubert Niewiadomski; Piotr Buciak; Henry Selvaraj; Piotr Sapiecha; Tadeusz Luba (DSD, 2003)

A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple Voltages. - Ling Wang 004; Henry Selvaraj (DSD, 2003)

Comparison of Heuristic Algorithms for Variable Partitioning in Circuit Implementation. - Muthukumar Venkatesan; Henry Selvaraj (VLSI Design, 2003)

Hybrid Greedy/Face Routing for Ad-Hoc Sensor Network. - Jianhong Li; Laxmi P. Gewali; Henry Selvaraj; Muthukumar Venkatesan (DSD, 2004)

Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms. - Mariusz Rawski; Henry Selvaraj; Pawel Morawiecki (DSD, 2004)

A Hybrid Approach to a Classification Problem. - Piotr Sapiecha; Henry Selvaraj; Jaroslaw Tomasz Stanczak; Krzysztof Sep; Tadeusz Luba (Intelligent Information Systems, 2004)

Synthesis scheme for low power designs with multiple supply voltages by tabu search. - Ling Wang 004; Yingtao Jiang; Henry Selvaraj (ISCAS (5), 2004)

Synthesis Scheme for Low Power Designs with Multiple Supply Voltages by Heuristic Algorithms. - Ling Wang 004; Yingtao Jiang; Henry Selvaraj (ITCC (2), 2004)

Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures. - Mariusz Rawski; Pawel Tomaszewicz; Henry Selvaraj; Tadeusz Luba (DSD, 2005)

Efficient Application of Modern Logic Synthesis in FPGA-Based Designing of Information and Signal Processing Systems. - Henry Selvaraj; Pawel Tomaszewicz; Mariusz Rawski; Tadeusz Luba (ITCC (2), 2005)

Multiple voltage synthesis scheme for low power design under timing and resource constraints. - Ling Wang 004; Yingtao Jiang; Henry Selvaraj (Integr. Comput. Aided Eng., 2005)

Multiple voltage and frequency scheduling for power minimization. - Venkatesan Muthukumar; Bharath Radhakrishnan; Henry Selvaraj (J. Syst. Archit., 2005)

An application of functional decomposition in ROM-based FSM implementation in FPGA devices. - Mariusz Rawski; Henry Selvaraj; Tadeusz Luba (J. Syst. Archit., 2005)

Reconfigurable embedded systems: Synthesis, design and application. - Henry Selvaraj; Lech Józwiak (J. Syst. Archit., 2005)

Multilevel Synthesis of Finite State Machines Based on Symbolic Functional Decomposition. - Mariusz Rawski; Henry Selvaraj; Tadeusz Luba; Piotr Szotkowski (Int. J. Comput. Intell. Appl., 2006)

Functional Decomposition - the Value and Implication for Both Neural Networks and Digital Designing. - Henry Selvaraj; Piotr Sapiecha; Mariusz Rawski; Tadeusz Luba (Int. J. Comput. Intell. Appl., 2006)

Support Vector Machine Based Automatic Classification of Human Brain Using MR Image Features. - Henry Selvaraj; S. Thamarai Selvi; D. Selvathi 001; R. Ramkumar (Int. J. Comput. Intell. Appl., 2006)

Abnormality Detection in Brain MR Images Using Minimum Error Thresholding Method. - D. Selvathi 001; S. Thamarai Selvi; Henry Selvaraj (Int. J. Comput. Intell. Appl., 2006)

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages. - Ling Wang 004; Yingtao Jiang; Henry Selvaraj (J. Supercomput., 2006)

Interference Aware Routing in Sensor Network. - Min Tun; Laxmi P. Gewali; Henry Selvaraj (ITNG, 2007)

Scheduling and optimal voltage selection with multiple supply voltages under resource constraints. - Ling Wang 004; Yingtao Jiang; Henry Selvaraj (Integr., 2007)

Placement-Directed Behavioral Synthesis Scheme for Simultaneous Scheduling Binding and Partitioning with Resources Operating at Multiple Voltages. - Dongxin Wen; Ling Wang 004; Yingtao Jiang; Henry Selvaraj; Xiao-Zong Yang (Int. J. Comput. Their Appl., 2007)

An efficient variable partitioning approach for functional decomposition of circuits. - Venkatesan Muthukumar; Robert J. Bignall; Henry Selvaraj (J. Syst. Archit., 2007)

Iteration-Free Fractal Coding for Image Compression Using Genetic Algorithm. - A. R. Nadira Banu Kamal; S. Thamarai Selvi; Henry Selvaraj (Int. J. Comput. Intell. Appl., 2008)

Processor Allocation Problem for NoC-Based Chip Multiprocessors. - Dawid Zydek; Henry Selvaraj (ITNG, 2009)

Constrained Disjoint Paths in Geometric Networks. - Laxmi P. Gewali; Dan Mazzella; Henry Selvaraj (Int. J. Comput. Intell. Appl., 2009)

Editorial: Applications of Computational Intelligence. - Henry Selvaraj; S. Arivazhagan 001 (Int. J. Comput. Intell. Appl., 2009)

Synthesis of Processor Allocator for Torus-Based Chip MultiProcessors. - Dawid Zydek; Henry Selvaraj; Laxmi P. Gewali (ITNG, 2010)

Hybrid Approach for Brain Tumor Segmentation in Magnetic Resonance Images Using Cellular Neural Networks and Optimization Techniques. - D. Selvathi 001; Henry Selvaraj; S. Thamarai Selvi (Int. J. Comput. Intell. Appl., 2010)

Hardware implementation of processor allocation schemes for mesh-based chip multiprocessors. - Dawid Zydek; Henry Selvaraj (Microprocess. Microsystems, 2010)

Ear-Slicing and Quality Triangulation. - Bartosz Kajak; Laxmi P. Gewali; Henry Selvaraj (ICSEng, 2011)

Extended Analysis of Resource Assignment in Modern Chip Multiprocessors. - Dawid Zydek; Grzegorz Chmaj; Henry Selvaraj (ICSEng, 2011)

Energy characteristic of a processor allocator and a network-on-chip. - Dawid Zydek; Henry Selvaraj; Grzegorz Borowik; Tadeusz Luba (Int. J. Appl. Math. Comput. Sci., 2011)

Fast and efficient processor allocation algorithm for torus-based chip multiprocessors. - Dawid Zydek; Henry Selvaraj (Comput. Electr. Eng., 2011)

Supervised Classification of White Blood Cells by Fusion of Color Texture Features and Neural Network. - G. Wiselin Jiji; Henry Selvaraj; G. Evelin Suji (Int. J. Comput. Intell. Appl., 2011)

Overlay-NoC and H-Phy based computing using modern Chip Multiprocessors. - Grzegorz Chmaj; Dawid Zydek; Yehia Zakarya Elhalwagy; Henry Selvaraj (EIT, 2012)

Accelerating High Performance Computing Applications: Using CPUs, GPUs, Hybrid CPU/GPU, and FPGAs. - Bin Liu; Dawid Zydek; Henry Selvaraj; Laxmi P. Gewali (PDCAT, 2012)

Tracker-Node Model for Energy Consumption in Reconfigurable Processing Systems. - Grzegorz Chmaj; Henry Selvaraj; Laxmi P. Gewali (ICSS, 2013)

A Survey of High Level Synthesis Languages, Tools, and Compilers for Reconfigurable High Performance Computing. - Luka Daoud; Dawid Zydek; Henry Selvaraj (ICSS, 2013)

Matrix Multiplication in Multiphysics Systems Using CUDA. - Dawid Krol; Dawid Zydek; Henry Selvaraj (ICSS, 2013)

Fast FPGA-based fault injection tool for embedded processors. - Mohammad Shokrolah Shirazi; Brendan Morris; Henry Selvaraj (ISQED, 2013)

Distributed Processing Applications for UAV/drones: A Survey. - Grzegorz Chmaj; Henry Selvaraj (ICSEng, 2014)

UAV Cooperative Data Processing Using Distributed Computing Platform. - Grzegorz Chmaj; Henry Selvaraj (ICSEng, 2014)

A Survey on Design and Implementation of Floating Point Adder in FPGA. - Luka Daoud; Dawid Zydek; Henry Selvaraj (ICSEng, 2014)

Energy-efficient distributed computing solutions for Internet of Things with ZigBee devices. - Grzegorz Chmaj; Henry Selvaraj (ICIS, 2015)

Concentrated mesh and fat tree usage efficiency in System-on-Chip based multiprocessor distributed processing architectures. - Grzegorz Chmaj; Henry Selvaraj (MECO, 2015)

FPGA Implementation of Fuzzy Inference System Based Edge Detection Algorithm. - D. Selvathi 001; Henry Selvaraj; J. Dharani (Int. J. Comput. Intell. Appl., 2015)

Energy-Efficient Computing Solutions for Internet of Things with ZigBee Reconfigurable Devices. - Grzegorz Chmaj; Henry Selvaraj (Int. J. Softw. Innov., 2016)

Interconnection Networks Efficiency in System-on-Chip Distributed Computing System: Concentrated Mesh and Fat Tree. - Grzegorz Chmaj; Henry Selvaraj (ICSEng, 2017)

Improved Genetic Algorithm for Finite-Horizon Optimal Control of Nonlinear Systems. - Ahmed Khamis; Dawid Zydek; Henry Selvaraj (ICSEng, 2017)

Analog and Mixed-Signal Verification Using Satisfiability Solver on Discretized Models. - Henry Selvaraj; Nikita Ramesh Wanjale (ICSEng, 2017)

FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals. - D. Selvathi 001; Henry Selvaraj (ICSEng, 2017)

A Novel Optimized Context-Based Deep Architecture for Scene Parsing. - Ranju Mandal; Brijesh K. Verma; Basim Azam; Henry Selvaraj (ICONIP (6), 2022)

Sensor failure mitigation in RTOS based internet of things (IoT) systems using machine learning. - Saugat Sharma; Grzegorz Chmaj; Henry Selvaraj (J. Parallel Distributed Comput., 2025)