Java threads - Java 2 (2. ed.). - Scott Oaks; Henry Wong (O'Reilly, 1999)

Jini in a nutshell - a desktop quick reference. - Scott Oaks; Henry Wong (O'Reilly, 2000)

Java threads - understanding and mastering concurrent programming: covers J2SE 5.o (3. ed.). - Scott Oaks; Henry Wong (O'Reilly, 2004)

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. - Henry Wong; Anne Bracy; Ethan Schuchman; Tor M. Aamodt; Jamison D. Collins; Perry H. Wang; Gautham N. Chinya; Ankur Khandelwal Groen; Hong Jiang; Hong Wang 003 (PACT, 2008)

Analyzing CUDA workloads using a detailed GPU simulator. - Ali Bakhoda; George L. Yuan; Wilson W. L. Fung; Henry Wong; Tor M. Aamodt (ISPASS, 2009)

Demystifying GPU microarchitecture through microbenchmarking. - Henry Wong; Misel-Myrto Papadopoulou; Maryam Sadooghi-Alvandi; Andreas Moshovos (ISPASS, 2010)

Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. - Henry Wong; Vaughn Betz; Jonathan Rose (FPGA, 2011)

Implications of Historical Trends in the Electrical Efficiency of Computing. - Jonathan G. Koomey; Stephen Berard; Marla Sanchez; Henry Wong (IEEE Ann. Hist. Comput., 2011)

Efficient methods for out-of-order load/store execution for high-performance soft processors. - Henry Wong; Vaughn Betz; Jonathan Rose (FPT, 2013)

Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. - Henry Wong; Vaughn Betz; Jonathan Rose (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. - Henry Wong; Vaughn Betz; Jonathan Rose (FCCM, 2016)

Assessing design dependencies in modular systems. - Henry Wong; Sana Ullah Qaisar; Michael J. Ryan (SysCon, 2016)

Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. - Henry Wong; Vaughn Betz; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2016)

High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. - Henry Wong; Vaughn Betz; Jonathan Rose (ACM Trans. Reconfigurable Technol. Syst., 2018)

A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. - Marc-Andre LaCroix; Henry Wong; Yun Hua Liu; Huong Ho; Semyon Lebedev; Petar Krotnev; Dorin Alexandru Nicolescu; Dmitry Petrov; Carlos Carvalho; Stephen Alie; Euhan Chong; Faisal Ahmed Musa; et al. (ISSCC, 2019)

MMW Radar-Based Technologies in Autonomous Driving: A Review. - Taohua Zhou; Mengmeng Yang 001; Kun Jiang 002; Henry Wong; Diange Yang (Sensors, 2020)

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. - Ming Yang 005; Shayan Shahramian; Hossein Shakiba; Henry Wong; Peter Krotnev; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. - Ming Yang 005; Shayan Shahramian; Henry Wong; Peter Krotnev; Anthony Chan Carusone (ISCAS, 2021)

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. - Marc-Andre LaCroix; Euhan Chong; Weilun Shen; Ehud Nir; Faisal Ahmed Musa; Haitao Mei 002; Mohammad-Mahdi Mohsenpour; Semyon Lebedev; Babak Zamanlooy; Carlos Carvalho; Qian Xin; Dmitry Petrov; et al. (ISSCC, 2021)

HD-Map Aided LiDAR-INS Extrinsic Calibration. - Henry Wong; Xiaolong Zhang; Tuopu Wen; Mengmeng Yang 001; Kun Jiang 002; Diange Yang (ITSC, 2021)