Methoden der VLSI-Implementierungen für Graphikanwendungen. - Herbert Grünbacher (Austrographics, 1988)

JAPROC - An 8 bit Micro Controller Design and Its Test Environment. - Herbert Grünbacher; Alexander Jaud (FPL, 1992)

Petri Nets Modeling in Pipelined Microprocessor Design. - Qian Zhang; Herbert Grünbacher (Application and Theory of Petri Nets, 1993)

VHDL-Based Rapid Hardware Prototyping Using FPGA Technology. - Maziar Khosravipour; Herbert Grünbacher (FPL, 1995)

WinDLX and MIPSim Pipeline Simulators for Teaching Computer Architecture. - Herbert Grünbacher; Maziar Khosravipour (ECBS, 1996)

Fast Carrier and Phase Synchronization Units for Digital Receivers Based on Re-configurable Logic. - Alfred Blaickner; O. Nagy; Herbert Grünbacher (FPL, 2000)

On re-configurable methods and gate array based solutions of fast forward error correction systems for software radio and set-top-box applications. - Alfred Blaickner; Herbert Grünbacher (IEEE Trans. Consumer Electron., 2000)

TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol. - Manfred Ley; Herbert Grünbacher (ICCD, 2002)

A scaleable instruction buffer for a configurable DSP core. - Christian Panis; Michael Bramberger; Herbert Grünbacher; Jari Nurmi (ESSCIRC, 2003)

xLIW - a scaleable long instruction word. - Christian Panis; Raimund Leitner; Herbert Grünbacher; Jari Nurmi (ISCAS (5), 2003)

xICU - in interrupt control unit for a configurable DSP core. - Christian Panis; J. Hohl; Herbert Grünbacher; Jari Nurmi (SoC, 2003)

A Branch File for a Configurable DSP Core. - Christian Panis; Gunther Laure; Wolfgang Lazian; Herbert Grünbacher; Jari Nurmi (VLSI, 2003)

A scalable instruction buffer and align unit for xDSPcore. - Christian Panis; Herbert Grünbacher; Jari Nurmi (IEEE J. Solid State Circuits, 2004)