Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits. - Johan S. Witters; Guido Groeseneken; Herman E. Maes (IEEE J. Solid State Circuits, 1989)

Novel level-identifying circuit for flash multilevel memories. - Donato Montanari; Jan Van Houdt; Guido Groeseneken; Herman E. Maes (IEEE J. Solid State Circuits, 1998)

Nonvolatile multilevel memories for digital applications. - Bruno Riccò; Guido Torelli; Massimo Lanzoni; Alessandro Manstretta; Herman E. Maes; Donato Montanari; Alberto Modelli (Proc. IEEE, 1998)

Simulation of 0.35 μm/0.25 μm CMOS Technology Doping Profiles. - M. Lorenzini; Luc Haspeslagh; Jan Van Houdt; Herman E. Maes (VLSI Design, 2001)

An easy-to-use mismatch model for the MOS transistor. - Jeroen A. Croon; Maarten Rosmeulen; Stefaan Decoutere; Willy Sansen; Herman E. Maes (IEEE J. Solid State Circuits, 2002)

High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices. - Vesselin K. Vassilev; Snezana Jenei; Guido Groeseneken; Rafael Venegas; Steven Thijs; Vincent De Heyn; M. Natarajan Iyer; Michiel Steyaert; Herman E. Maes (Microelectron. Reliab., 2003)

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits. - Vesselin K. Vassilev; Vladislav A. Vashchenko; Philippe Jansen; B.-J. Choi; Ann Concannon; J.-J. Yang; Guido Groeseneken; M. I. Natarajan; Marcel ter Beek; Peter Hopper; Michiel Steyaert; Herman E. Maes (Microelectron. Reliab., 2004)

ESD-RF co-design methodology for the state of the art RF-CMOS blocks. - Vesselin K. Vassilev; Steven Thijs; P. L. Segura; Piet Wambacq; Paul Leroux; Guido Groeseneken; M. I. Natarajan; Herman E. Maes; Michiel Steyaert (Microelectron. Reliab., 2005)

NBTI reliability of Ni FUSI/HfSiON gates: Effect of silicide phase. - A. Shickova; Ben Kaczer; Anabela Veloso; Marc Aoulaiche; M. Houssa; Herman E. Maes; Guido Groeseneken; J. A. Kittl (Microelectron. Reliab., 2007)