High frequency jitter estimator for SoCs. - Hervé Le Gall; Rshdee Alhakim; Miroslav Valka; Salvador Mir; Haralampos-G. D. Stratigopoulos; Emmanuel Simeu (ETS, 2015)

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times. - Haralampos-G. D. Stratigopoulos; Manuel J. Barragán; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (ITC, 2015)

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques. - Manuel J. Barragán; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Des. Test, 2016)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC. - Manuel J. Barragán; Rshdee Alhakim; Haralampos-G. D. Stratigopoulos; Matthieu Dubois; Salvador Mir; Hervé Le Gall; Neha Bhargava; Ankur Bal (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology. - Hani Malloug; Manuel J. Barragan Asian; Salvador Mir; Laurent Basteres; Hervé Le Gall (ETS, 2017)