Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Christophe Forel (ETS, 2012)

Reduced code linearity testing of pipeline adcs in the presence of noise. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (VTS, 2013)

Reduced-Code Linearity Testing of Pipeline ADCs. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet; Gerard Bret (IEEE Des. Test, 2013)

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique. - Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Naudet (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs. - Guillaume Renaud; Manuel J. Barragán; Asma Laraba; Haralampos-G. D. Stratigopoulos; Salvador Mir; Hervé Le Gall; Hervé Naudet (J. Electron. Test., 2016)