Efficient system level cache architecture for multimedia SoC. - Prashant Karandikar; Mihir N. Mody; Hetul Sanghvi; Vasant Easwaran; Prithvi Shankar; Rahul Gulati; Niraj Nandan; Subrangshu Das (ICACCI, 2014)

High performance and flexible imaging Sub-system. - Mihir N. Mody; Hetul Sanghvi; Niraj Nandan; Shashank Dabral; Rajasekhar Allu; Dharmendra Soni; Sunil Sah; Gayathri Seshadri; Prashant Karandikar (ICACCI, 2014)

A monolithic programmable Ultra-HD video codec engine. - Hetul Sanghvi; Mihir N. Mody; Niraj Nandan; Mahesh Mehendale; Subrangshu Das; Dipan Kumar Mandal; Nainala Vyagrheswarudu; Vijayavardhan Baireddy; Pavan Shastry (ICASSP, 2014)

2D cache architecture for motion compensation in a 4K Ultra-HD AVC and HEVC video codec system. - Hetul Sanghvi (ICCE, 2014)

A 28nm programmable and low power ultra-HD video codec engine. - Hetul Sanghvi; Mihir N. Mody; Niraj Nandan; Mahesh Mehendale; Subrangshu Das; Dipan Kumar Mandal; Pavan Shastry (ISCAS, 2014)

Customization of de-blocking filter edge order for high performance: Study of H.264 AVC/SVC, H.265. - Niraj Nandan; Mihir N. Mody; Hetul Sanghvi; Prithvi Shankar (ISSPIT, 2014)

Image signal processing for front camera based automated driver assistance system. - Mihir Mody; Niraj Nandan; Shashank Dabral; Hetul Sanghvi; Rajat Sagar; Zoran Nikolic; Kedar Chitnis; Rajasekhar Allu; Gang Hua 003 (ICCE-Berlin, 2015)

Accelerating H.264/HEVC video slice processing using application specific instruction set processor. - Dipan Kumar Mandal; Mihir Mody; Mahesh Mehendale; Naresh Yadav; Ghone Chaitanya; Piyali Goswami; Hetul Sanghvi; Niraj Nandan (ICCE, 2015)

Flexible Wide Dynamic Range (WDR) processing support in image signal processor (ISP). - Mihir N. Mody; Niraj Nandan; Hetul Sanghvi; Rajasekhar Allu; Rajat Sagar (ICCE, 2015)

Efficient VLSI architecture for SAO decoding in 4K Ultra-HD HEVC video codec. - Mihir N. Mody; Niraj Nandan; Hetul Sanghvi (SoCC, 2016)

A 216 GOPS flexible WDR Image Processor for ADAS SoC. - Mihir N. Mody; Hetul Sanghvi; Niraj Nandan; Shashank Dabral; Rajasekhar Allu; Rajat Sagar; Kedar Chitnis; Jason Jones; Brijesh Jadhav; Sujith Shivalingappa; Aish Dubey (COOL Chips, 2017)

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. - Hassan Dbouk; Hetul Sanghvi; Mahesh Mehendale; Naresh R. Shanbhag (ECCV (27), 2020)

2.6 A 16nm 3.5B+ Transistor >14TOPS 2-to-10W Multicore SoC Platform for Automotive and Embedded Applications with Integrated Safety MCU, 512b Vector VLIW DSP, Embedded Vision and Imaging Acceleration. - Rama Venkatasubramanian; Don Steiss; Greg Shurtz; Tim Anderson; Kai Chirca; Raghavendra Santhanagopal; Niraj Nandan; Anish Reghunath; Hetul Sanghvi; Daniel Wu; Abhijeet Chachad; Brian Karguth; et al. (ISSCC, 2020)

Novel Census Transform Hardware IP. - Anish Reghunath; Mihir Mody; Hetul Sanghvi; Ankur (VLSID, 2021)

An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. - Avishek Biswas; Hetul Sanghvi; Mahesh Mehendale; G. Preet (CICC, 2022)