A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. - Kyehyun Kyung; Hi-Choon Lee; Ki-Whan Song; Ho-Sung Song; Keewook Jung; Joon-Seo Moon; Byoung-Sul Kim; Sung-Burn Cho; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration. - Changsik Yoo; Kye-Hyun Kyung; Kyunam Lim; Hi-Choon Lee; Joon-Wan Chai; Nak-Won Heo; Dong-Jin Lee; Chang-Hyun Kim (IEEE J. Solid State Circuits, 2004)