An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

Higher-level representation of local spatio-temporal features for human action recognition using Subspace Matching Kernels. - Bisser Raytchev; Hideaki Kawamoto; Toru Tamaki; Kazufumi Kaneda (ICPR, 2016)