A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. - Hirotoshi Sato; Hideaki Nagaoka; Hiroaki Honda; Yukio Maki; Tomohisa Wada; Yutaka Arita; Kazuhito Tsutsumi; Makoto Taniguchi; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)