An elastic pipeline mechanism by self-timed circuits. - Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Katsuhiko Asada; Hiroaki Terada (IEEE J. Solid State Circuits, 1988)

VLSI implementation of a variable-length pipeline scheme for data-driven processors. - Tetsuo Yamasaki; Kenji Shima; Shinji Komori; Hidehiro Takata; Toshiyuki Tamura; Fumiyasu Asai; Takio Ohno; Osamu Tomisawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. - Shinji Komori; Hidehiro Takata; Todhixuki Tamura; Fumixsdu Asai; Takio Ohno; Osamu Tomisawa; Tetsuo Yamasaki; Kenji Shima; Hiroaki Nishikawa; Hiroaki Terada (IEEE J. Solid State Circuits, 1989)

Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system. - Mitsumasa Koyanagi; Hidehiro Takata; Hiroki Mori; Junichiro Iba (IEEE J. Solid State Circuits, 1990)

A 100-mega-access per second matching memory for a data-driven microprocessor. - Hidehiro Takata; Shinji Komori; Toshiyuki Tamura; Fumiyasu Asai; Hisakazu Sato; Takio Ohno; Takeshi Tokuda; Hiroki Nishikawa; Hirofumi Terada (IEEE J. Solid State Circuits, 1990)

A Data-Driven Architecture for Distributed Parallel Processing. - Toshiyuki Tamura; Shinji Komori; Fumiyasu Asai; Hirono Tsubota; Hisakazu Sato; Hidehiro Takata; Yoshihiro Seguchi; Takeshi Tokuda; Hiroaki Terada (ICCD, 1991)

A real-time digital VCR encode/decode and MPEG-2 decode LSI implemented on a dual-issue RISC processor. - Atsushi Mohri; Akira Yamada 005; Y. Yoshida; Hisakazu Sato; Hidehiro Takata; K. Nakakimura; M. Hashizume; Y. Shimotsuma; K. Tsuchihashi (IEEE J. Solid State Circuits, 1999)

The D30V/MPEG multimedia processor. - Hidehiro Takata; Tetsuya Watanabe; Tetsuo Nakajima; Takashi Takagaki; Hisakazu Sato; Atsushi Mohri; Akira Yamada 005; Toshiki Kanamoto; Yoshio Matsuda; Shuhei Iwade; Yasutaka Horiba (IEEE Micro, 1999)

A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; et al. (CICC, 2001)

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)

A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. - Niichi Itoh; Yasumasa Tsukamoto; Takeshi Shibagaki; Koji Nii; Hidehiro Takata; Hiroshi Makino (ISCAS (1), 2005)

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. - Mitsuya Fukazawa; Tetsuro Matsuno; Toshifumi Uemura; Rei Akiyama; Tetsuya Kagemoto; Hiroshi Makino; Hidehiro Takata; Makoto Nagata (ISSCC, 2007)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. - Kazutami Arimoto; Toshihiro Hattori; Hidehiro Takata; Atsushi Hasegawa; Toru Shimizu (IEICE Trans. Electron., 2007)

Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (DAC, 2008)

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. - Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara (ISLPED, 2008)

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. - Mitsuya Fukazawa; Masanori Kurimoto; Rei Akiyama; Hidehiro Takata; Makoto Nagata (IEICE Trans. Electron., 2009)

Misleading energy and performance claims in sub/near threshold digital systems. - Yu Pu; Xin Zhang 025; Jim Huang; Atsushi Muramatsu; Masahiro Nomura; Koji Hirairi; Hidehiro Takata; Taro Sakurabayashi; Shinji Miyano; Makoto Takamiya; Takayasu Sakurai (ICCAD, 2010)

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (ACM Trans. Design Autom. Electr. Syst., 2010)

Decoupling capacitance boosting for on-chip resonant supply noise reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (DDECS, 2011)

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (ESSCIRC, 2011)

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2011)

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction. - Jinmyoung Kim; Toru Nakura; Hidehiro Takata; Koichiro Ishibashi; Makoto Ikeda; Kunihiro Asada (IEICE Trans. Electron., 2012)

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation. - Takuya Sawada; Taku Toshikawa; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEICE Trans. Electron., 2012)

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. - Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

An Extended Direct Power Injection Method for In-Place Susceptibility Characterization of VLSI Circuits Against Electromagnetic Interference. - Takuya Sawada; Kumpei Yoshikawa; Hidehiro Takata; Koji Nii; Makoto Nagata (IEEE Trans. Very Large Scale Integr. Syst., 2015)