Automatic placement algorithms for high packing density V L S I. - Tokinori Kozawa; Hidekazu Terai; Tatsuki Ishii; Michiyoshi Hayase; Chihei Miura; Yasushi Ogawa; Kuniaki Kishida; Norio Yamada; Yasuhiro Ohno (DAC, 1983)

Combine and top down block placement algorithm for hierarchical logic VLSI layout. - Tokinori Kozawa; Chihei Miura; Hidekazu Terai (DAC, 1984)

A routing procedure for mixed array of custom macros and standard cells. - Hidekazu Terai; Michiyoshi Hayase; Tokinori Kozawa (DAC, 1985)

Research in Design Automation for VLSI Layout. - Tokinori Kozawa; Hidekazu Terai (IEEE Des. Test, 1985)

Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs. - Yasushi Ogawa; Tatsuki Ishii; Yoichi Shiraishi; Hidekazu Terai; Tokinori Kozawa; Kyoji Yuyama; Kyoji Chiba (DAC, 1986)

Automatic Layout Procedures for Serial Routing Devices. - Yasushi Ogawa; Hidekazu Terai; Tokinori Kozawa (DAC, 1988)

Basic Concepts of Timing-oriented Design Automation for High-performance Mainframe Computers. - Hidekazu Terai; Fumio Goto; Katsuro Wakai; Tokinori Kozawa; Mitsugu Edagawa; Satoshi Hososaka; Masahiro Hashimoto (DAC, 1991)

Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1. - Hidekazu Terai; Kazutoshi Gemma; Yohsuke Nagao; Yasuo Satoh; Yasuhiro Ohno (DAC, 1994)

Scalable GA processor architecture and its implementation of processor-element. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ICASSP, 2002)

VLSI processor architecture for real-time GA processing and PE-VLSI design. - Tetsuya Imai; Masaya Yoshikawa; Hidekazu Terai; Hironori Yamauchi (ISCAS (3), 2004)

Performance driven placement technique based on collaboration of software and hardware. - Masaya Yoshikawa; Hidekazu Terai (Congress on Evolutionary Computation, 2005)

Hybrid genetic algorithm engine for high-speed floorplanning. - Masaya Yoshikawa; Hidekazu Terai (ECCTD, 2005)

A Hierarchical Parallel Placement Technique based on Genetic Algorithm. - Masaya Yoshikawa; Hidekazu Terai (ISDA, 2005)

Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique. - Masaya Yoshikawa; Hidekazu Terai (SERA, 2005)

Co-evolutionary robotics using two kinds of neural networks. - Masaya Yoshikawa; Hidekazu Terai (CAINE, 2006)

Immune Algorithm Processor. - Masaya Yoshikawa; Masahiro Fukui; Hidekazu Terai (CATA, 2006)

Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing. - Masaya Yoshikawa; Hidekazu Terai (SERA, 2006)

Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation. - Masaya Yoshikawa; Hidekazu Terai (J. Adv. Comput. Intell. Intell. Informatics, 2006)

Architecture for high-speed Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (IRI, 2007)

The new DFM approach based on a genetic algorithm. - Masaya Yoshikawa; Hidekazu Terai (Artif. Life Robotics, 2007)

Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption. - Masaya Yoshikawa; Hidekazu Terai (J. Adv. Comput. Intell. Intell. Informatics, 2007)

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (GEM, 2008)

Route selection algorithm based on integer operation Ant Colony Optimization. - Masaya Yoshikawa; Hidekazu Terai (IRI, 2008)

Hybrid Architecture of Genetic Algorithm and Simulated Annealing. - Masaya Yoshikawa; Hironori Yamauchi; Hidekazu Terai (Eng. Lett., 2008)

Car Navigation System Based on Hybrid Genetic Algorithm. - Masaya Yoshikawa; Hidekazu Terai (CSIE (5), 2009)

OX Hardware Engine for High Speed Character Inheritance. - Masaya Yoshikawa; Hidekazu Terai (GEM, 2009)

Dedicated Hardware for Ant Colony Optimization Using Distributed Memory. - Masaya Yoshikawa; Hidekazu Terai (ITNG, 2009)