A DSP line equalizer VLSI for TCM digital subscriber-line transmission. - Hideki Ando; Masao Nakaya; Hiroki Hona; Ihuo Iizuka; Yasutaka Horiba (IEEE J. Solid State Circuits, 1988)

Speculative Execution and Reducing Branch Penalty in a Parallel Issue Machine. - Hideki Ando; Chikako Nakanishi; Hirohisa Machida; Tetsuya Hara; Satoru Kishida; Masao Nakaya (ICCD, 1993)

A VLSI chip set for a large-scale parallel inference machine: PIM/m. - Hirohisa Machida; Hideki Ando; Kenichi Yasuda; Kiyohiro Furutani; Yukihiro Yamashita; Hiroshi Nakashima; Yasutaka Takeda; Katsuto Nakajima; Masayoshi Sakao; Masao Nakaya (IEEE J. Solid State Circuits, 1993)

Unconstrained Speculative Execution with Predicated State Buffering. - Hideki Ando; Chikako Nakanishi; Tetsuya Hara; Masao Nakaya (ISCA, 1995)

Code scheduling on a superscalar processor: SARCH. - Chikako Nakanishi; Hideki Ando; Hirohisa Machida; Masao Nakaya (Syst. Comput. Jpn., 1995)

Performance Comparison of ILP Machines with Cycle Time Evaluation. - Tetsuya Hara; Hideki Ando; Chikako Nakanishi; Masao Nakaya (ISCA, 1996)

Software pipelining with path selection. - Chikako Nakanishi; Hideki Ando; Tetsuya Hara; Masao Nakaya (Syst. Comput. Jpn., 1998)

An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. - Ryotaro Kobayashi; Yukihiro Ogawa; Hideki Ando; Toshio Shimada; Mitsuaki Iwata (EUROMICRO, 1999)

Distributed memoryless point convergence algorithm for mobile robots with limited visibility. - Hideki Ando; Yoshinobu Oasa; Ichiro Suzuki; Masafumi Yamashita (IEEE Trans. Robotics Autom., 1999)

A preactivating mechanism for a VT-CMOS cache using address prediction. - Ryo Fujioka; Kiyokazu Katayama; Ryotaro Kobayashi; Hideki Ando; Toshio Shimada (ISLPED, 2002)

Pipeline stage unification: a low-energy consumption technique for future mobile processors. - Hajime Shimada; Hideki Ando; Toshio Shimada (ISLPED, 2003)

Limits of Thread-Level Parallelism in Non-numerical Programs. - Akio Nakajima; Ryotaro Kobayashi; Hideki Ando; Toshio Shimada (Inf. Media Technol., 2006)

Data prefetching and address pre-calculation through instruction pre-execution with two-step physical register deallocation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (MEDEA@PACT, 2007)

Two-Step Physical Register Deallocation for Data Prefetching and Address Pre-Calculation. - Akihiro Yamamoto; Yusuke Tanaka 001; Hideki Ando; Toshio Shimada (Inf. Media Technol., 2008)

Reducing register file size through instruction pre-execution enhanced by value prediction. - Yusuke Tanaka 001; Hideki Ando (ICCD, 2009)

Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation. - Kazunaga Hyodo; Kengo Iwamoto; Hideki Ando (IEICE Trans. Inf. Syst., 2009)

Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction. - Yusuke Tanaka 001; Hideki Ando (IEICE Trans. Inf. Syst., 2010)

Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path. - Kyohei Yamaguchi; Yuya Kora; Hideki Ando (ICCD, 2011)

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification. - Kyohei Yamaguchi; Yuya Kora; Hideki Ando (IEICE Trans. Inf. Syst., 2012)

MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP. - Yuya Kora; Kyohei Yamaguchi; Hideki Ando (MICRO, 2013)

Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. - Ryota Shioya; Hideki Ando (ICCD, 2014)

A Front-End Execution Architecture for High Energy Efficiency. - Ryota Shioya; Masahiro Goshima; Hideki Ando (MICRO, 2014)

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism. - Yuya Kora; Kyohei Yamaguchi; Hideki Ando (IEICE Trans. Inf. Syst., 2014)

Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. - Hideki Ando; Ryota Shioya (IEICE Trans. Inf. Syst., 2016)

Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. - Ryota Shioya; Hideki Ando (IEICE Trans. Inf. Syst., 2016)

FXA: Executing Instructions in Front-End for Energy Efficiency. - Ryota Shioya; Ryo Takami; Masahiro Goshima; Hideki Ando (IEICE Trans. Inf. Syst., 2016)

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. - Yasumasa Chidai; Kojiro Izuoka; Ryota Shioya; Masahiro Goshima; Hideki Ando (ARCS, 2018)

Rearranging Random Issue Queue with High IPC and Short Delay. - Shinji Sakai; Taishi Suenaga; Ryota Shioya; Hideki Ando (ICCD, 2018)

Performance Improvement by Prioritizing the Issue of the Instructions in Unconfident Branch Slices. - Hideki Ando (MICRO, 2018)

Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. - Keita Doi; Ryota Shioya; Hideki Ando (J. Inf. Process., 2018)

SWQUE: A Mode Switching Issue Queue with Priority-Correcting Circular Queue. - Hideki Ando (MICRO, 2019)

Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. - Reoma Matsuo; Ryota Shioya; Hideki Ando (IEEE Comput. Archit. Lett., 2019)

Segmenting Age Matrices to Improve Instruction Scheduling without Increasing Delay and Area. - Hideki Ando (ICCD, 2022)

Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. - Yasutaka Matsuda; Ryota Shioya; Hideki Ando (IEICE Trans. Inf. Syst., 2022)

Localizing the Tag Comparisons in the Wakeup Logic to Reduce Energy Consumption of the Issue Queue. - Kenichiro Mori; Sota Kosugi; Hiroto Yoshida; Hajime Shimada; Hideki Ando (MICRO, 2024)