Network analysis by hierarchical tearing method. - Hideki Asai; Shinsaku Mori (Syst. Comput. Jpn., 1985)

Special parallel processor for lu decomposition of a large-scale sparse matrix. - Hideki Asai; Mitsuo Asai; Mamoru Tanaka (Syst. Comput. Jpn., 1987)

Transient Simulation of Coupled Lossy Interconnects by Window Partitioning Technique. - Vijaya Gopal Bandi; Hideki Asai (ISCAS, 1994)

Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits. - Masaki Ishida; Koichi Hayashi; Masakatsu Nishigaki; Hideki Asai (ISCAS, 1994)

Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace. - Masakatsu Nishigaki; Nobuyuki Tanaka; Hideki Asai (ISCAS, 1994)

Relaxation-Based Steady-State Analysis of Single- and Multi-Conductor Transmission Lines in Frequency Domain. - Takeshi Senoo; Hiroaki Makino; Hideki Asai (ISCAS, 1994)

A study of Hopfield neural networks with external noises. - Hideki Asai; Katsuaki Onodera; Takeshi Kamio; Hiroshi Ninomiya (ICNN, 1995)

Neural network approach to traveling salesman problem based on hierarchical city adjacency. - Hiroshi Ninomiya; Kazumichi Sato; Takeshi Nakayama; Hideki Asai (ICNN, 1995)

Convergence of Hopfield Neural Network for Orthogonal Transformation. - Takeshi Kamio; Hiroshi Ninomiya; Hideki Asai (ISCAS, 1995)

Orthogonalized Steepest Descent Method for Solving Nonlinear Equations. - Hiroshi Ninomiya; Hideki Asai (ISCAS, 1995)

DESIRE3T+: waveform relaxation-based simulator for coupled lossy transmission lines circuits. - Takayuki Watanabe; Hideki Asai (ICECS, 1996)

Tiling algorithm with fitting violation function for analog neural array. - Hideki Asai; Takeshi Nakayama; Hiroshi Ninomiya (ICNN, 1996)

Design and implementation of neuro-based discrete Walsh transform processor. - Takeshi Kamio; Hiroshi Ninomiya; Hideki Asai (ICNN, 1996)

Design and implementation of neural network logic circuits with global convergence. - Hiroshi Ninomtya; Kunitaka Egawa; Takeshi Kamio; Hideki Asai (ICNN, 1996)

Application of neuro-based optimization algorithm to three dimensional cylindric puzzles. - Hiroyuki Yamamoto; Takeshi Nakayama; Hiroshi Ninomiya; Hideki Asai (ICNN, 1997)

Neural network simulator for spatiotemporal pattern analysis. - Atsushi Kamo; Hiroshi Ninomiya; Teru Yoneyama; Hideki Asai (ICECS, 1998)

SPADE : analog/digital mixed signal simulator with analog hardware description language. - Hiroshi Sagesaka; Hisashi Irii; Hideki Asai (ICECS, 1998)

Transient analysis for high-speed interconnect networks based on AWE and delay evaluation technique. - Takayuki Watanabe; Hideki Asai (ICECS, 1998)

Design method of neural networks for limit cycle generator. - Teru Yoneyama; Hiroshi Ninomiya; Hideki Asai (IJCNN, 1999)

Expanded GMC for transient analysis of transmission line networks. - Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (6), 1999)

Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. - Takayuki Watanabe; Hideki Asai (ISCAS (6), 1999)

Design Method of Limit Cycle Generator by Hysteresis Neural Networks. - Teru Yoneyama; Hideki Asai; Hiroshi Ninomiya (IJCNN (3), 2000)

Neuro-Based Human-Face Recognition with 2-Dimensional Discrete Walsh Transform. - Masahiro Yoshida; Hideki Asai; Takeshi Kamio (IJCNN (3), 2000)

Simulation for the optimal placement of decoupling capacitors on printed circuit board. - Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (3), 2001)

High-speed interconnect simulation using MIMO type of adaptive least square method. - Masaya Suzuki; Hirofumi Miyashita; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (5), 2001)

Two floating resistor circuits and their applications to synaptic weights in analog neural networks. - Shashidhar Tantry; Teru Yoneyama; Hideki Asai (ISCAS (1), 2001)

A Neuro-Based Optimization Algorithm for Tiling Problems with Rotation. - Shinsuke Manabe; Hideki Asai (Neural Process. Lett., 2001)

A low voltage floating resistor having positive and negative resistance values. - Shashidhar Tantry; Takao Oura; Teru Yoneyama; Hideki Asai (APCCAS (1), 2002)

Optimal placement of decoupling capacitors on PCB using Poynting vectors obtained by FDTD method. - I. Hattori; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (5), 2002)

Noise analysis of power/ground planes on PCB by SPICE-like simulator with model order reduction technique. - Hidemasa Kubota; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (5), 2002)

A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. - Takao Oura; Teru Yoneyama; Shashidhar Tantry; Hideki Asai (ISCAS (3), 2002)

An Efficient Simulator for Multiport Interconnects with Model Order Reduction Technique. - Hidemasa Kubota; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A CMOS Floating Resistor Circuit Having Both Positive and Negative Resistance Values. - Takao Oura; Teru Yoneyama; Shashidhar Tantry; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Design and Simulation of 4Q-Multiplier Using Linear and Saturation Regions of MOSFET Complementally. - Tsutomu Suzuki; Takao Oura; Teru Yoneyama; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. - Kenichi Suzuki; Mitsuhiro Takeda; Atsushi Kamo; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Behavioral modeling of EM devices by selective orthogonal matrix least-squares method. - Yuichi Tanji; Masaya Suzuki; Takayuki Watanabe; Hideki Asai (ASP-DAC, 2003)

An efficient learning algorithm with second-order convergence for multilayer neural networks. - Hiroshi Ninomiya; Chikahiro Tomita; Hideki Asai (IJCNN, 2003)

Analysis of PCB interconnects using electromagnetic reduction technique. - Takayuki Watanabe; Hideki Asai (ISCAS (3), 2003)

A Low Voltage Floating Resistor Circuit Having Both Positive and Negative Resistance Values. - Shashidhar Tantry; Yasuyuki Hiraku; Takao Oura; Teru Yoneyama; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A Framework for Macromodeling and Mixed-Mode Simulation of Circuits/Interconnects and Electromagnetic Radiations. - Takayuki Watanabe; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Face Image Recognition by 2-Dimensional Discrete Walsh Transform and Multi-Layer Neural Network. - Masahiro Yoshida; Takeshi Kamio; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Closed-form expressions of distributed RLC interconnects for analysis of on-chip inductance effects. - Yuichi Tanji; Hideki Asai (DAC, 2004)

Hybrid Reduction Technique for Efficient Simulation of Linear/Nonlinear Mixed Circuits. - Takashi Mine; Hidemasa Kubota; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (DATE, 2004)

Three dimensional module packing by simulated annealing. - Hirokazu Yamagishi; Hiroshi Ninomiya; Hideki Asai (Congress on Evolutionary Computation, 2005)

Generalized method of the time-domain circuit simulation based on LIM with MNA formulation. - Hidemasa Kubota; Yuichi Tanji; Takayuki Watanabe; Hideki Asai (CICC, 2005)

Interconnect simulation using FDTD method with variable mesh size technique. - Hirofumi Suzuki; Hidemasa Kubota; Takayuki Watanabe; Hideki Asai (ECCTD, 2005)

Optimization procedure of class E amplifiers using SPICE. - Yuichi Tanji; Hiroo Sekiya; Hideki Asai (ECCTD, 2005)

An efficient learning algorithm for finding multiple solutions based on fixed-point homotopy method. - Hiroshi Ninomiya; Chikahiro Tomita; Hideki Asai (IJCNN, 2005)

Modified hybrid reduction technique for the simulation of linear/nonlinear mixed circuits. - Takashi Mine; Hidemasa Kubota; Atsushi Kamo; Takayuki Watanabe; Hideki Asai (ISCAS (5), 2005)

Modeling of power distribution networks with signal lines for SPICE simulators. - Takayuki Watanabe; Hideki Asai (ISCAS (6), 2005)

New Criteria of Selective Orthogonal Matrix Least-Squares Method for Macromodeling Multiport Networks Characterized by Sampled Data. - Yuichi Tanji; Masaya Suzuki; Takayuki Watanabe; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Parallel-distributed time-domain circuit simulation of power distribution networks with frequency-dependent parameters. - Takayuki Watanabe; Yuichi Tanji; Hidemasa Kubota; Hideki Asai (ASP-DAC, 2006)

Two-staged Tabu Search for Floorplan Problem Using O-Tree Representation. - Hiroshi Ninomiya; Kimihiko Numayama; Hideki Asai (IEEE Congress on Evolutionary Computation, 2006)

Concurrent Design of Delta-Sigma Modulator Using Behavioral Modeling and Simulation with the Verilog-A. - Takafumi Yamamoto; Tsutomu Suzuki; Hideki Asai (CICC, 2006)

Large scale RLC circuit analysis using RLCG-MNA formulation. - Yuichi Tanji; Takayuki Watanabe; Hidemasa Kubota; Hideki Asai (DATE, 2006)

Fast timing analysis of plane circuits via two-layer CNN-based modeling. - Yuichi Tanji; Hideki Asai; Masayoshi Oda; Yoshifumi Nishio; Akio Ushida (ISCAS, 2006)

Quasi-One-Step Gauss-Jacobi Method for Large-Scale Interconnect Analysis via RLCG-MNA Formulation. - Yuichi Tanji; Takayuki Watanabe; Hidemasa Kubota; Hideki Asai (ISQED, 2006)

An Enhanced Time-Domain Circuit Simulation Technique Based on LIM. - Hidemasa Kubota; Yuichi Tanji; Takayuki Watanabe; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A fast transient simulation based on Model Order Reduction and RLCG-MNA formulation. - Akira Tsuzaki; Toshio Unno; Yuichi Tanji; Hideki Asai (ECCTD, 2007)

Application of Relaxation-Based Technique to ADI-FDTD Method and Its Estimation. - Yuya Nakazono; Hideki Asai (ISCAS, 2007)

Fast Transient Simulation of Power Distribution Networks Containing Dispersion Based on Parallel-Distributed Leapfrog Algorithm. - Takayuki Watanabe; Yuichi Tanji; Hidemasa Kubota; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Generating stable and sparse reluctance/inductance matrix under insufficient conditions. - Yuichi Tanji; Takayuki Watanabe; Hideki Asai (ASP-DAC, 2008)

Acceleration of ADI-FDTD Method by Gauss-Seidel Relaxation Approach. - Yuya Nakazono; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane. - Tadatoshi Sekine; Yuichi Tanji; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Fast Simulation Technique of Plane Circuits via Two-Layer CNN-Based Modeling. - Yuichi Tanji; Hideki Asai; Masayoshi Oda; Yoshifumi Nishio; Akio Ushida (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

CMOS Circuit Simulation Using Latency Insertion Method. - Tadatoshi Sekine; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition. - Shuichi Aono; Masaki Unno; Hideki Asai (ASP-DAC, 2010)

Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. - Takayuki Watanabe; Hideki Asai (DATE, 2010)

An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit. - Yuji Okazaki; Takanori Uno; Hideki Asai (IEICE Trans. Electron., 2010)

An Approach for Practical Use of Common-Mode Noise Reduction Technique for In-Vehicle Electronic Equipment. - Takanori Uno; Kouji Ichikawa; Yuichi Mabuchi; Atsushi Nakamura; Yuji Okazaki; Hideki Asai (IEICE Trans. Commun., 2010)

Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. - Hiroki Kurobe; Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2012)

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. - Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2013)

HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. - Takahiro Takasaki; Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2014)

Foreword. - Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

SI/PI/EMI simulation techniques and application to automotive electronic design issues. - Hideki Asai (MIXDES, 2017)

Implementation of a Modified Nesterov's Accelerated Quasi-Newton Method on Tensorflow. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Hideki Asai (ICMLA, 2018)

A Stochastic Variance Reduced Nesterov's Accelerated Quasi-Newton Method. - Sota Yasuda; Shahrzad Mahboubi; S. Indrapriyadarsini; Hiroshi Ninomiya; Hideki Asai (ICMLA, 2019)

A Stochastic Quasi-Newton Method with Nesterov's Accelerated Gradient. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Hideki Asai (ECML/PKDD (1), 2019)

Momentum Acceleration of Quasi-Newton Training for Neural Networks. - Shahrzad Mahboubi; S. Indrapriyadarsini; Hiroshi Ninomiya; Hideki Asai (PRICAI (2), 2019)

An Adaptive Stochastic Nesterov Accelerated Quasi Newton Method for Training RNNs. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Hideki Asai (CoRR, 2019)

A Neural Network Approach to Analog Circuit Design Optimization using Nesterov's Accelerated Quasi-Newton Method. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (ISCAS, 2020)

A Nesterov's Accelerated quasi-Newton method for Global Routing using Deep Reinforcement Learning. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (CoRR, 2020)

A modified limited memory Nesterov's accelerated quasi-Newton. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (CoRR, 2021)

On the Practical Robustness of the Nesterov's Accelerated Quasi-Newton Method. - S. Indrapriyadarsini; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (AAAI, 2022)

A Stochastic Momentum Accelerated Quasi-Newton Method for Neural Networks (Student Abstract). - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (AAAI, 2022)

Accelerating Symmetric Rank-1 Quasi-Newton Method with Nesterov's Gradient for Training Neural Networks. - S. Indrapriyadarsini; Shahrzad Mahboubi; Hiroshi Ninomiya; Takeshi Kamio; Hideki Asai (Algorithms, 2022)