A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line. - Satoshi Eto; Masato Matsumiya; Masato Takita; Yuki Ishii; Toshikazu Nakamura; Kuninori Kawabata; Hideki Kano; Ayako Kitamoto; Toshimi Ikeda; Toru Koga; Mitsuhiro Higashiho; Yuji Serizawa; et al. (IEEE J. Solid State Circuits, 1998)

A 43-Gb/s full-rate-clock 4: 1 multiplexer in InP-based HEMT technology. - Yasuhiro Nakasha; Toshihide Suzuki; Hideki Kano; Kouji Tsukashima; Akio Ohya; Ken Sawada; Kozo Makiyama; Tsuyoshi Takahashi; Masahiro Nishi; Tatsuya Hirose; Masahiko Takikawa; Yuu Watanabe (IEEE J. Solid State Circuits, 2002)

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets. - Kouichi Kanda; Yoichi Kawano; Takao Sasaki; Noriaki Shirai; Tetsuro Tamura; Shigeaki Kawai; Masahiro Kudo; Tomotoshi Murakami; Hiroyuki Nakamoto; Nobumasa Hasegawa; Hideki Kano; Nobuhiro Shimazui; et al. (ISSCC, 2012)

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Seitaro Kawai; Shinji Yamaura; et al. (ISSCC, 2014)

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Shigeaki Kawai; Kazuo Suto; et al. (IEEE J. Solid State Circuits, 2014)

A 28-Gb/s 4.5-pJ/bit transceiver with 1-tap decision feedback equalizer in 28-nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Tomoyuki Arai; Yutaka Ide; Kazuhiro Terashima; Hirohito Higashi; Tomokazu Higuchi; et al. (A-SSCC, 2015)

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS. - Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Shigeaki Kawai; Tomoyuki Arai; Hirohito Higashi; et al. (ISSCC, 2016)

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS. - Hiroki Miyaoka; Futoshi Terasawa; Masahiro Kudo; Hideki Kano; Atsushi Matsuda; Noriaki Shirai; Shigeaki Kawai; Takayuki Shibasaki; Takumi Danjo; Yuuki Ogata; Yasufumi Sakai; Hisakatsu Yamaguchi; et al. (VLSI Circuits, 2016)