A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel. - Ken Miyauchi; Kazuya Mori; Toshinori Otaka; Toshiyuki Isozaki; Naoto Yasuda; Alex Tsai; Yusuke Sawai; Hideki Owada; Isao Takayanagi; Junichi Nakamura (Sensors, 2020)

An Area-Efficient up/down Double-Sampling Circuit for a LOFIC CMOS Image Sensor. - Ai Otani; Hiroaki Ogawa; Ken Miyauchi; Sangman Han; Hideki Owada; Isao Takayanagi; Shunsuke Okura (Sensors, 2023)

An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor. - Ai Otani; Hiroaki Ogawa; Ken Miyauchi; Yuki Morikawa; Hideki Owada; Isao Takayanagi; Shunsuke Okura (ISCAS, 2025)