A CMOS multichannel 10-Gb/s transceiver. - Hideki Takauchi; Hirotaka Tamura; Satoshi Matsubara; Masaya Kibune; Yoshiyasu Doi; Takaya Chiba; Hideaki Anbutsu; Hisakatsu Yamaguchi; Toshihiko Mori; Motomu Takatsu; Kohtaroh Gotoh; Toshiaki Sakai; et al. (IEEE J. Solid State Circuits, 2003)

A 0.8-1.3V 16-channel 2.5Gb/s high-speed serial transceiver in a 90nm standard CMOS process. - Yoshiyasu Doi; Syunitirou Masaki; Takaya Chiba; Hirohito Higashi; Hisakatsu Yamaguchi; Hideki Takauchi; Hideki Ishida; Kohtaroh Gotoh; Junji Ogawa; Hirotaka Tamura (CICC, 2005)

A 5-6.4-Gb/s 12-channel transceiver with pre-emphasis and equalization. - Hirohito Higashi; Syunitirou Masaki; Masaya Kibune; Satoshi Matsubara; Takaya Chiba; Yoshiyasu Doi; Hisakatsu Yamaguchi; Hideki Takauchi; Hideki Ishida; Kohtaroh Gotoh; Hirotaka Tamura (IEEE J. Solid State Circuits, 2005)

3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Seitaro Kawai; Shinji Yamaura; et al. (ISSCC, 2014)

A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. - Takayuki Shibasaki; Win Chaivipas; Yanfei Chen; Yoshiyasu Doi; Takayuki Hamada; Hideki Takauchi; Toshihiko Mori; Yoichi Koyanagi; Hirotaka Tamura (VLSIC, 2014)

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE. - Kazuaki Oishi; Eiji Yoshida; Yasufumi Sakai; Hideki Takauchi; Yoichi Kawano; Noriaki Shirai; Hideki Kano; Masahiro Kudo; Tomotoshi Murakami; Tetsuro Tamura; Shigeaki Kawai; Kazuo Suto; et al. (IEEE J. Solid State Circuits, 2014)