Repeater insertion method and its application to a 300MHz 128-bit 2-way superscalar microprocessor. - Norman Kojima; Yukiko Parameswar; Christian Klingner; Yukio Ohtaguro; Masataka Matsui; Shigeaki Iwasa; Tatsuo Teruyama; Takayoshi Shimazawa; Hideki Takeda; Kouji Hashizume; Haruyuki Tago; Masaaki Yamada (ASP-DAC, 2000)

A single-chip MPEG-2 codec based on customizable media microprocessor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (CICC, 2002)

Visconti: multi-VLIW image recognition processor based on configurable processor [obstacle detection applications]. - Jun Tanahe; Yasuhiro Taniguchi; Takashi Miyamori; Yukimasa Miyamoto; Hideki Takeda; Masaya Tarui; Hiromitsu Nakayama; Nohuyulu Takeda; Kenichi Maeda; Masataka Matsui (CICC, 2003)

A single-chip MPEG-2 codec based on customizable media embedded processor. - Shunichi Ishiwata; Tomoo Yamakage; Yoshiro Tsuboi; Takayoshi Shimazawa; Tomoko Kitazawa; Shuji Michinaka; Kunihiko Yahagi; Hideki Takeda; Akihiro Oue; Tomoya Kodama; Nobu Matsumoto; Takayuki Kamei; et al. (IEEE J. Solid State Circuits, 2003)

A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding. - Shen Li; Takeshi Ikenaga; Hideki Takeda; Masataka Matsui; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. - Toshihide Fujiyoshi; Shinichiro Shiratake; Shuou Nomura; Tsuyoshi Nishikawa; Yoshiyuki Kitasho; Hideho Arakida; Yuji Okuda; Yoshiro Tsuboi; Mototsugu Hamada; Hiroyuki Hara; Tetsuya Fujita; Fumitoshi Hatori; et al. (IEEE J. Solid State Circuits, 2006)

When to stop reviewing documents in eDiscovery cases: the Lit i View quality monitor and endpoint detector. - Jakob Halskov; Hideki Takeda (MEDES, 2013)