Video signal processor configuration by multiprocessor approach. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Masakatsu Yamashina; Tadayoshi Enomoto (ICASSP, 1986)

Realtime video signal processor module. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (ICASSP, 1987)

A single-board video signal processor module employing newly developed LSI devices. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (IEEE J. Sel. Areas Commun., 1988)

A microprogrammable real-time video signal processor (VSP) for motion compensation. - Masakazu Yamashina; Tadayoshi Enomoto; Takemitsu Kunio; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Takao Nishitani; Masao Satoh; Koichi Kikuchi (IEEE J. Solid State Circuits, 1988)

Parallel video signal processor configuration based on overlap-save technique and its LSI processor element: VISP. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Toshiyuki Kanou; Koichi Kikuchi (J. VLSI Signal Process., 1989)

A real-time software programmable processor for HDTV and stereo scope signals. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Mitsuharu Yano (ASAP, 1990)

Background separation/filtering for videophone applications. - Hidenobu Harasaki; Mitsuharu Yano; Takao Nishitani (ICASSP, 1990)

A real-time HDTV signal processor: HD-VSP. - Ichiro Tamitani; Hidenobu Harasaki; Takao Nishitani (IEEE Trans. Circuits Syst. Video Technol., 1991)

A simplified motion estimation using an approximation for the MPEG-2 real-time encoder. - Yuzo Senda; Hidenobu Harasaki; Mitsuharu Yano (ICASSP, 1995)

Theoretical background and improvement of a simplified half-pel motion estimation. - Yuzo Senda; Hidenobu Harasaki; Mitsuharu Yano (ICIP (3), 1996)

A realtime software MPEG transcoder using a novel motion vector reuse and a SIMD optimization techniques. - Yuzo Senda; Hidenobu Harasaki (ICASSP, 1999)

High performance and cost effective memory architecture for an HDTV decoder LSI. - Tetsuro Takizawa; Junji Tajime; Hidenobu Harasaki (ICASSP, 1999)

Memory Compression Method Considering Memory Bandwidth for Hdtv Decoder Lsis. - Junji Tajime; Tetsuro Takizawa; Satoshi Nogaki; Hidenobu Harasaki (ICIP (2), 1999)