A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. - Akira Tanabe; Toshio Takeshima; Hiroki Koike; Yoshiharu Aimoto; Masahide Takada; Toshiyuki Ishijima; Naoki Kasai; Hiromitsu Hada; Kentaro Shibahara; Takemitsu Kunio; Takaho Tanigawa; Takanori Saeki; et al. (IEEE J. Solid State Circuits, 1992)

An embedded FeRAM macro cell for a smart card microcontroller. - Tohru Miwa; Junichi Yamada; Yuji Okamoto; Hiroki Koike; Hideo Toyoshiina; Hiromitsu Hada; Yoshihiro Hayashi; Hiroaki Oliizaki; Yoichi Miyasalca; Takemitsu Kunio; Hidenobu Miyamoto; Hideki Gomi; et al. (CICC, 1998)

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications. - Muneo Fukaishi; Satoshi Nakamura; Akio Tajima; Yasushi Kinoshita; Yoshihiko Suemura; Hisamitsu Suzuki; Toshiro Itani; Hidenobu Miyamoto; Naoya Henmi; Tohru Yamazaki; Michio Yotsuyanagi (IEEE J. Solid State Circuits, 1999)

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme. - Yasuhiro Takai; Mamoru Fujita; Kyoichi Nagata; Satoshi Isa; Shigeyuki Nakazawa; Atsunori Hirobe; Hiroaki Ohkubo; Masato Sakao; Shinichi Horiba; Tadashi Fukase; Yoshihiro Takaishi; Makoto Matsuo; et al. (IEEE J. Solid State Circuits, 2000)