Balanced 3-phase analog signal processing for radio communications. - Takafumi Yamaji; Tetsuro Itakura; Rui Ito; Takeshi Ueno; Hidenori Okuni (ISCAS, 2006)

A Direct Conversion Receiver with Fast-Settling DC Offset Canceller. - Hidenori Okuni; Rui Ito; Hiroshi Yoshida; Tetsuro Itakura (PIMRC, 2007)

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface. - Hiroshi Yoshida; Takehiko Toyoda; T. Yasuda; Yosuke Ogasawara; M. Ishii; T. Murasaki; Gaku Takemura; Masaomi Iwanaga; T. Takida; Yuta Araki; T. Hashimoto; K. Sami; et al. (ESSCIRC, 2008)

950 MHz, -60 dB TX-Cancellation Active Directional Couplers for UHF RFID Application. - Fumi Moritsuka; Hidenori Okuni; Toshiyuki Umeda (IEICE Trans. Electron., 2011)

20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication. - Shigehito Saigusa; Toshiya Mitomo; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Shusuke Kawai; Tong Wang 018; Masanori Furuta; Kei Shiraishi; Koichiro Ban; Seiichiro Horikawa; Tomoya Tandai; et al. (ISSCC, 2014)

A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS. - Masanori Furuta; Hidenori Okuni; Masahiro Hosoya; Akihide Sai; Junya Matsuno; Shigehito Saigusa; Tetsuro Itakura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS. - Hidenori Okuni; Akihide Sai; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (ISSCC, 2016)

19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC. - Akihide Sai; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Masanori Furuta; Tetsuro Itakura (ISSCC, 2016)

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS. - Akihide Sai; Hidenori Okuni; Tuan Thanh Ta; Satoshi Kondo; Takashi Tokairin; Masanori Furuta; Tetsuro Itakura (IEEE J. Solid State Circuits, 2016)

A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; Tomohiro Koizumi; et al. (ISSCC, 2018)

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. - Kentaro Yoshioka; Hiroshi Kubota; Tomonori Fukushima; Satoshi Kondo; Tuan Thanh Ta; Hidenori Okuni; Kaori Watanabe; Masatoshi Hirono; Yoshinari Ojima; Katsuyuki Kimura; Sohichiroh Hosoda; Yutaka Ota; et al. (IEEE J. Solid State Circuits, 2018)

5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (ISSCC, 2020)

A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR. - Tuan Thanh Ta; Hiroshi Kubota; Koichi Kokubun; Toshiki Sugimoto; Masatoshi Hirono; Mitsuhiro Sengoku; Hisaaki Katagiri; Hidenori Okuni; Satoshi Kondo; Shinichi Ohtsuka; Honam Kwon; Keita Sasaki; et al. (VLSI Circuits, 2020)

An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm2 Voltage/Time Dual-Data-Converter-Based AFE. - Satoshi Kondo; Hiroshi Kubota; Hisaaki Katagiri; Yutaka Ota; Masatoshi Hirono; Tuan Thanh Ta; Hidenori Okuni; Shinichi Ohtsuka; Yoshinari Ojima; Tomohiko Sugimoto; Hirotomo Ishii; Kentaro Yoshioka; et al. (IEEE J. Solid State Circuits, 2020)

Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections. - Kentaro Yoshioka; Hidenori Okuni; Tuan Thanh Ta; Akihide Sai (IROS, 2021)