Design of Diagnosable Sequential Machines Utilizing Extra Outputs. - Hideo Fujiwara; Kozo Kinoshita (IEEE Trans. Computers, 1974)

Easily Testable Sequential Machines with Extra Inputs. - Hideo Fujiwara; Yoich Nagao; Tsutomu Sasao; Kozo Kinoshita (IEEE Trans. Computers, 1975)

LORES - Logic Reorganization System. - Shunichiro Nakamura; Shinichi Murai; Chiyoji Tanaka; Masayuki Terai; Hideo Fujiwara; Kozo Kinoshita (DAC, 1978)

On the Computational Complexity of System Diagnosis. - Hideo Fujiwara; Kozo Kinoshita (IEEE Trans. Computers, 1978)

Connection Assignments for Probabilistically Diagnosable Systems. - Hideo Fujiwara; Kozo Kinoshita (IEEE Trans. Computers, 1978)

Some Existence Theorems for Probabilistically Diagnosable Systems. - Hideo Fujiwara; Kozo Kinoshita (IEEE Trans. Computers, 1978)

On Closedness and Test Complexity of Logic Circuits. - Hideo Fujiwara (IEEE Trans. Computers, 1981)

A Design of Programmable Logic Arrays with Universal Tests. - Hideo Fujiwara; Kozo Kinoshita (IEEE Trans. Computers, 1981)

The Complexity of Fault Detection Problems for Combinational Logic Circuits. - Hideo Fujiwara; Shunichi Toida (IEEE Trans. Computers, 1982)

Test generation for scan design circuits with tri-state modules and bidirectional terminals. - Takuji Ogihara; Shinichi Murai; Yuzo Takamatsu; Kozo Kinoshita; Hideo Fujiwara (DAC, 1983)

On the Acceleration of Test Generation Algorithms. - Hideo Fujiwara; Takeshi Shimono (IEEE Trans. Computers, 1983)

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. - Kewal K. Saluja; Kozo Kinoshita; Hideo Fujiwara (IEEE Trans. Computers, 1983)

Design for Testability for Complete Test Coverage. - Akira Motohara; Hideo Fujiwara (IEEE Des. Test, 1984)

A New PLA Design for Universal Testability. - Hideo Fujiwara (IEEE Trans. Computers, 1984)

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. - Hideo Fujiwara; Kewal K. Saluja; Kozo Kinoshita (ITC, 1985)

Implementing a Built-In Self-Test PLA Design. - Robert P. Treuer; Hideo Fujiwara; Vinod K. Agarwal (IEEE Des. Test, 1985)

Design for testability and built-in self-test for VLSI circuits. - Hideo Fujiwara (Microprocess. Microsystems, 1986)

A random-pattern testable design for programmable logic arrays. - Hideo Fujiwara (Syst. Comput. Jpn., 1987)

A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. - Robert P. Treuer; Vinod K. Agarwal; Hideo Fujiwara (IEEE Trans. Computers, 1987)

Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. - Hideo Fujiwara; Osamu Fujisawa; Kazunori Hikone (ITC, 1988)

Test research in Japan. - Hideo Fujiwara; Yuzo Takamatsu; Takashi Nanya; Teruhiko Yamada; Hideo Tamamoto; Kiyoshi Furuya (IEEE Des. Test, 1988)

A design of programmable logic arrays with random pattern-testability. - Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Enhancing random-pattern coverage of programmable logic arrays via masking technique. - Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Three-valued neural networks for test generation. - Hideo Fujiwara (FTCS, 1990)

Computational Complexity of Controllability/Observability Problems for Combinational Circuits. - Hideo Fujiwara (IEEE Trans. Computers, 1990)

Optimal granularity of test generation in a distributed system. - Hideo Fujiwara; Tomoo Inoue (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

An Efficient Test Generation Algorithm Based on Search State Dominance. - Takayuki Fujino; Hideo Fujiwara (FTCS, 1992)

A Search Space Pruning Method for Test Pattern Generation using Search State Dominance. - Takayuki Fujino; Hideo Fujiwara (J. Circuits Syst. Comput., 1993)

Parity-scan design to reduce the cost of test application. - Hideo Fujiwara; Akihiro Yamamoto (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

A method of search space pruning based on search state dominance. - Takayuki Fujino; Hideo Fujiwara (Syst. Comput. Jpn., 1994)

Universal test complexity of field-programmable gate arrays. - Tomoo Inoue; Hideo Fujiwara; Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto (Asian Test Symposium, 1995)

A scheduling problem in test generation. - Tomoo Inoue; Hironori Maeda; Hideo Fujiwara (VTS, 1995)

Foreword. - Hideo Fujiwara (IEICE Trans. Inf. Syst., 1995)

An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images. - Akihiro Fujiwara; Toshimitsu Masuzawa; Hideo Fujiwara (Inf. Process. Lett., 1995)

Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System. - Hideo Fujiwara; Tomoo Inoue (IEEE Trans. Parallel Distributed Syst., 1995)

An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. - Tomoo Inoue; Toshimitsu Masuzawa; Hiroshi Youra; Hideo Fujiwara (Asian Test Symposium, 1996)

A Test Methodology for Interconnect Structures of LUT-based FPGAs. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Tomoo Inoue; Hideo Fujiwara (Asian Test Symposium, 1996)

A Snapshot Algorithm for Distributed Mobile Systems. - Yasuo Sato; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (ICDCS, 1996)

On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. - Tomoo Inoue; Satoshi Miyazaki; Hideo Fujiwara (Asian Test Symposium, 1997)

Testing for the programming circuit of LUT-based FPGAs. - Hiroyuki Michinishi; Tokumi Yokohira; Takuji Okamoto; Tomoo Inoue; Hideo Fujiwara (Asian Test Symposium, 1997)

Sequential Test Generation Based on Circuit Pseudo-Transformation. - Satoshi Ohtake; Tomoo Inoue; Hideo Fujiwara (Asian Test Symposium, 1997)

A Parallel Algorithm for Weighted Distance Transforms. - Akihiro Fujiwara; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (IPPS, 1997)

Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. - Michiko Inoue; Sen Moriya; Toshimitsu Masuzawa; Hideo Fujiwara (WDAG, 1997)

A latency-optimal superstabilizing mutual exclusion protocol. - Eiichiro Ueda; Yoshiaki Katayama; Toshimitsu Masuzawa; Hideo Fujiwara (WSS, 1997)

Parallel algorithms for connected-component problems of gray-scale images. - Akihiro Fujiwara; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 1997)

A sequential circuit structure with combinational test generation complexity and its application. - Hideo Fujiwara; Satoshi Ohtake; Tomoya Takasaki (Syst. Comput. Jpn., 1997)

Non-scan design for testable data paths using thru operation. - Katsuyuki Takabatake; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 1997)

Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults. - Daisuke Yoshida; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 1997)

An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. - Tomoo Inoue; Toshinori Hosokawa; Takahiro Mihara; Hideo Fujiwara (Asian Test Symposium, 1998)

A High-Level Synthesis Method for Weakly Testable Data Paths. - Michiko Inoue; Takeshi Higashimura; Kenji Noda; Toshimitsu Masuzawa; Hideo Fujiwara (Asian Test Symposium, 1998)

A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. - Satoshi Ohtake; Toshimitsu Masuzawa; Hideo Fujiwara (Asian Test Symposium, 1998)

SelfStabilizing WaitFree Clock Synchronization with Bounded Space. - Sen Moriya; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (OPODIS, 1998)

Needed: Third-generation ATPG Benchmarks. - Hideo Fujiwara (IEEE Des. Test Comput., 1998)

Universal Fault Diagnosis for Lookup Table FPGAs. - Tomoo Inoue; Satoshi Miyazaki; Hideo Fujiwara (IEEE Des. Test Comput., 1998)

An approach to test synthesis from higher level. - Michiko Inoue; Hideo Fujiwara (Integr., 1998)

Partial scan design methods based on internally balanced structure. - Tomoya Takasaki; Tomoo Inoue; Hideo Fujiwara (Syst. Comput. Jpn., 1998)

On the synthesis of synchronizable finite state machines with partial scan. - Hiroshi Youra; Tomoo Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 1998)

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. - Debesh Kumar Das; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 1999)

Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. - Toshinori Hosokawa; Toshihiro Hiraoka; Tomoo Inoue; Hideo Fujiwara (Asian Test Symposium, 1999)

A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. - Satoshi Ohtake; Michiko Inoue; Hideo Fujiwara (Asian Test Symposium, 1999)

A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. - Tomoya Takasaki; Hideo Fujiwara; Tomoo Inoue (Asian Test Symposium, 1999)

Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. - Takashi Ishimizu; Akihiro Fujiwara; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (ISPAN, 1999)

A cost optimal parallel algorithm for weighted distance transforms. - Akihiro Fujiwara; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Parallel Comput., 1999)

A non-scan DFT method at register-transfer level to achieve complete fault efficiency. - Satoshi Ohtake; Hiroki Wada; Toshimitsu Masuzawa; Hideo Fujiwara (ASP-DAC, 2000)

Spirit: satisfiability problem implementation for redundancy identification and test generation. - Emil Gizdarski; Hideo Fujiwara (Asian Test Symposium, 2000)

A class of sequential circuits with combinational test generation complexity under single-fault assumption. - Michiko Inoue; Emil Gizdarski; Hideo Fujiwara (Asian Test Symposium, 2000)

Strong self-testability for data paths high-level synthesis. - Xiaowei Li 001; Toshimitsu Masuzawa; Hideo Fujiwara (Asian Test Symposium, 2000)

Single-control testability of RTL data paths for BIST. - Toshimitsu Masuzawa; Minoru Izutsu; Hiroki Wada; Hideo Fujiwara (Asian Test Symposium, 2000)

Test Generation for Acyclic Sequential Circuits with Hold Registers. - Tomoo Inoue; Debesh Kumar Das; Chiiho Sano; Takahiro Mihara; Hideo Fujiwara (ICCAD, 2000)

Non-scan design for testability for synchronous sequential circuits based on conflict analysis. - Dong Xiang; Yi Xu; Hideo Fujiwara (ITC, 2000)

A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. - Hideo Fujiwara (VLSI Design, 2000)

Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. - Hiroki Wada; Toshimitsu Masuzawa; Kewal K. Saluja; Hideo Fujiwara (VLSI Design, 2000)

LFSR-Based Deterministic TPG for Two-Pattern Testing. - Xiaowei Li 001; Paul Y. S. Cheung; Hideo Fujiwara (J. Electron. Test., 2000)

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency. - Satoshi Ohtake; Toshimitsu Masuzawa; Hideo Fujiwara (J. Electron. Test., 2000)

A New Class of Sequential Circuits with Combinational Test Generation Complexity. - Hideo Fujiwara (IEEE Trans. Computers, 2000)

A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. - Satoshi Ohtake; Shintaro Nagai; Hiroki Wada; Hideo Fujiwara (ASP-DAC, 2001)

Design for Hierarchical Two-Pattern Testability of Data Paths. - Md. Altaf-Ul-Amin; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2001)

BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. - Ken-ichi Yamaguchi; Hiroki Wada; Toshimitsu Masuzawa; Hideo Fujiwara (Asian Test Symposium, 2001)

A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. - Tomokazu Yoneda; Hideo Fujiwara (Asian Test Symposium, 2001)

A Framework for Low Complexity Static Learning. - Emil Gizdarski; Hideo Fujiwara (DAC, 2001)

Testable Design of Sequential Circuits with Improved Fault Efficiency. - Debesh Kumar Das; Bhargab B. Bhattacharya; Satoshi Ohtake; Hideo Fujiwara (VLSI Design, 2001)

Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. - Michiko Inoue; Shinya Umetani; Toshimitsu Masuzawa; Hideo Fujiwara (DISC, 2001)

A causal broadcast protocol for distributed mobile systems. - Chikara Ohori; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 2001)

Design for Two-Pattern Testability of Controller-Data Path Circuits. - Atlaf Ul Amin; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2002)

Fault Set Partition for Efficient Width Compression. - Emil Gizdarski; Hideo Fujiwara (Asian Test Symposium, 2002)

A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. - Tomoo Inoue; Tomokazu Miura; Akio Tamura; Hideo Fujiwara (Asian Test Symposium, 2002)

Integrated Test Scheduling, Test Parallelization and TAMDesign. - Erik Larsson; Klas Arvidsson; Hideo Fujiwara; Zebo Peng (Asian Test Symposium, 2002)

Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. - Dong Xiang; Shan Gu; Hideo Fujiwara (Asian Test Symposium, 2002)

Power constrained preemptive TAM scheduling. - Erik Larsson; Hideo Fujiwara (ETW, 2002)

An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. - Michiko Inoue; Chikateru Jinno; Hideo Fujiwara (ICCD, 2002)

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. - Satoshi Ohtake; Hideo Fujiwara; Shunjiro Miwa (VTS, 2002)

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption. - Michiko Inoue; Emil Gizdarski; Hideo Fujiwara (J. Electron. Test., 2002)

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. - Tomokazu Yoneda; Hideo Fujiwara (J. Electron. Test., 2002)

A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings. - Yoshiaki Katayama; Eiichiro Ueda; Hideo Fujiwara; Toshimitsu Masuzawa (J. Parallel Distributed Comput., 2002)

A layout adjustment problem for disjoint rectangles preserving orthogonal order. - Kunihiko Hayashi; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 2002)

Test sequence compaction methods for acyclic sequential circuits using a time expansion model. - Toshinori Hosokawa; Tomoo Inoue; Toshihiro Hiraoka; Hideo Fujiwara (Syst. Comput. Jpn., 2002)

Parallel algorithms for selection on the BSP and BSP* models. - Takashi Ishimizu; Akihiro Fujiwara; Michiko Inoue; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 2002)

A nonscan DFT method for controllers to provide complete fault efficiency. - Satoshi Ohtake; Toshimitsu Masuzawa; Hideo Fujiwara (Syst. Comput. Jpn., 2002)

SPIRIT: a highly robust combinational test generation algorithm. - Emil Gizdarski; Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Handling the pin overhead problem of DFTs for high-quality and at-speed tests. - Dong Xiang; Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. - Toshinori Hosokawa; Hiroshi Date; Masahide Miyazaki; Michiaki Muraoka; Hideo Fujiwara (Asian Test Symposium, 2003)

Test Synthesis for Datapaths Using Datapath-Controller Functions. - Michiko Inoue; Kazuhiro Suzuki; Hiroyuki Okamoto; Hideo Fujiwara (Asian Test Symposium, 2003)

Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2003)

Optimal System-on-Chip Test Scheduling. - Erik Larsson; Hideo Fujiwara (Asian Test Symposium, 2003)

Software-Based Delay Fault Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (Asian Test Symposium, 2003)

Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. - Dong Xiang; Ming-Jing Chen; Jia-Guang Sun; Hideo Fujiwara (Asian Test Symposium, 2003)

Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. - Dong Xiang; Shan Gu; Hideo Fujiwara (Asian Test Symposium, 2003)

A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. - Satoshi Ohtake; Kouhei Ohtani; Hideo Fujiwara (DATE, 2003)

Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. - Tomokazu Yoneda; Tetsuo Uchiyama; Hideo Fujiwara (ITC, 2003)

Test Resource Partitioning and Optimization for SOC Designs. - Erik Larsson; Hideo Fujiwara (VTS, 2003)

Design for Consecutive Transparency of Cores in System-on-a-Chip. - Tomokazu Yoneda; Hideo Fujiwara (VTS, 2003)

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. - Dong Xiang; Yi Xu; Hideo Fujiwara (IEEE Trans. Computers, 2003)

Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. - Debesh Kumar Das; Tomoo Inoue; Susanta Chakraborty; Hideo Fujiwara (Asian Test Symposium, 2004)

Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. - Kazuko Kambe; Michiko Inoue; Hideo Fujiwara (Asian Test Symposium, 2004)

Classification of Sequential Circuits Based on ?k Notation. - Chia Yee Ooi; Hideo Fujiwara (Asian Test Symposium, 2004)

Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. - Zhiqiang You; Ken-ichi Yamaguchi; Michiko Inoue; Jacob Savir; Hideo Fujiwara (Asian Test Symposium, 2004)

An efficient scan tree design for test time reduction. - Yannick Bonhomme; Tomokazu Yoneda; Hideo Fujiwara; Patrick Girard 001 (ETS, 2004)

A design methodology to realize delay testable controllers using state transition information. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (ETS, 2004)

Instruction-Based Delay Fault Self-Testing of Processor Cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (VLSI Design, 2004)

Design & Test Education in Asia. - Debesh K. Das; Hideo Fujiwara; Yungang Li; Yinghua Min; Shiyi Xu; Yervant Zorian (IEEE Des. Test Comput., 2004)

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency. - Debesh Kumar Das; Satoshi Ohtake; Hideo Fujiwara (J. Electron. Test., 2004)

Preemptive System-on-Chip Test Scheduling. - Erik Larsson; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

A DFT Selection Method for Reducing Test Application Time of System-on-Chips. - Masahide Miyazaki; Toshinori Hosokawa; Hiroshi Date; Michiaki Muraoka; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2004)

Efficient test solutions for core-based designs. - Erik Larsson; Klas Arvidsson; Hideo Fujiwara; Zebo Peng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A Class of Linear Space Compactors for Enhanced Diagnostic. - Thomas Clouqueur; Hideo Fujiwara; Kewal K. Saluja (Asian Test Symposium, 2005)

An Effective Design for Hierarchical Test Generation Based on Strong Testability. - Hideyuki Ichihara; Tomoo Inoue; Naoki Okamoto; Toshinori Hosokawa; Hideo Fujiwara (Asian Test Symposium, 2005)

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. - Hiroyuki Iwata; Tomokazu Yoneda; Satoshi Ohtake; Hideo Fujiwara (Asian Test Symposium, 2005)

Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. - Kazuko Kambe; Michiko Inoue; Hideo Fujiwara; Tsuyoshi Iwagaki (Asian Test Symposium, 2005)

Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. - Dong Xiang; Ming-Jing Chen; Hideo Fujiwara (Asian Test Symposium, 2005)

Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. - Dong Xiang; Kaiwei Li; Hideo Fujiwara (Asian Test Symposium, 2005)

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. - Tomokazu Yoneda; Hisakazu Takakuwa; Hideo Fujiwara (Asian Test Symposium, 2005)

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. - Yuki Yoshikawa; Satoshi Ohtake; Michiko Inoue; Hideo Fujiwara (Asian Test Symposium, 2005)

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (ETS, 2005)

Testing Superscalar Processors in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (FPL, 2005)

Instruction-based delay fault self-testing of pipelined processor cores. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (ISCAS (6), 2005)

Design and analysis of multiple weight linear compactors of responses containing unknown values. - Thomas Clouqueur; Kamran Zarrineh; Kewal K. Saluja; Hideo Fujiwara (ITC, 2005)

Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. - Yoshiyuki Nakamura; Jacob Savir; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

Classification of Sequential Circuits Based on tauk Notation and Its Applications. - Chia Yee Ooi; Thomas Clouqueur; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

Delay Fault Testing of Processor Cores in Functional Mode. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. - Zhiqiang You; Ken-ichi Yamaguchi; Michiko Inoue; Jacob Savir; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

Improving test effectiveness of scan-based BIST by scan chain partitioning. - Dong Xiang; Ming-Jing Chen; Jia-Guang Sun; Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A memory grouping method for sharing memory BIST logic. - Masahide Miyazaki; Tomokazu Yoneda; Hideo Fujiwara (ASP-DAC, 2006)

Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture. - Hideo Fujiwara; Jiaguang Sun; Krishnendu Chakrabarty; Yang Zhao 001; Dong Xiang (ATS, 2006)

Design for Testability of Software-Based Self-Test for Processors. - Masato Nakazato; Satoshi Ohtake; Michiko Inoue; Hideo Fujiwara (ATS, 2006)

A New Scan Design Technique Based on Pre-Synthesis Thru Functions. - Chia Yee Ooi; Hideo Fujiwara (ATS, 2006)

Power-constrained test scheduling for multi-clock domain SoCs. - Tomokazu Yoneda; Kimihiko Masuda; Hideo Fujiwara (DATE, 2006)

Electrical Behavior of GOS Fault affected Domino Logic Cell. - Mariane Comte; Satoshi Ohtake; Hideo Fujiwara; Michel Renovell (DELTA, 2006)

Low-Cost Hardening of Image Processing Applications Against Soft Errors. - Ilia Polian; Bernd Becker 001; Masato Nakasato; Satoshi Ohtake; Hideo Fujiwara (DFT, 2006)

Power-Constrained SOC Test Schedules through Utilization of Functional Buses. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (ICCD, 2006)

A New Class of Sequential Circuits with Acyclic Test Generation Complexity. - Chia Yee Ooi; Hideo Fujiwara (ICCD, 2006)

Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. - Dong Xiang; Kaiwei Li; Hideo Fujiwara; Jiaguang Sun (ICCD, 2006)

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (VLSI-SoC, 2006)

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation. - Tsuyoshi Iwagaki; Satoshi Ohtake; Hideo Fujiwara (VLSI-SoC (Selected Papers), 2006)

BIST Pretest of ICs: Risks and Benefits. - Yoshiyuki Nakamura; Jacob Savir; Hideo Fujiwara (VTS, 2006)

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips. - Masahide Miyazaki; Tomokazu Yoneda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

Error Identification in At-Speed Scan BIST Environment in the Presence of Circuit and Tester Speed Mismatch. - Yoshiyuki Nakamura; Thomas Clouqueur; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

Effect of BIST Pretest on IC Defect Level. - Yoshiyuki Nakamura; Jacob Savir; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

A Low Power Deterministic Test Using Scan Chain Disable Technique. - Zhiqiang You; Tsuyoshi Iwagaki; Michiko Inoue; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

Design for consecutive transparency method of RTL circuits. - Tomokazu Yoneda; Hideo Fujiwara (Syst. Comput. Jpn., 2006)

System-on-chip test scheduling with reconfigurable core wrappers. - Erik Larsson; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. - Virendra Singh; Michiko Inoue; Kewal K. Saluja; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (ASP-DAC, 2007)

Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. - Dan Zhao; Unni Chandran; Hideo Fujiwara (ASP-DAC, 2007)

Fault-dependent/independent Test Generation Methods for State Observable FSMs. - Toshinori Hosokawa; Ryoichi Inoue; Hideo Fujiwara (ATS, 2007)

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Hideo Fujiwara (ATS, 2007)

Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost. - Dong Xiang; Krishnendu Chakrabarty; Dianwei Hu; Hideo Fujiwara (ATS, 2007)

Test Scheduling for Memory Cores with Built-In Self-Repair. - Tomokazu Yoneda; Yuusuke Fukuda; Hideo Fujiwara (ATS, 2007)

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. - Yuki Yoshikawa; Satoshi Ohtake; Hideo Fujiwara (ATS, 2007)

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (ATS, 2007)

Multi-Frequency Modular Testing of SoCs by Dynamically Reconfiguring Multi-Port ATE. - Dan Zhao; Ronghua Huang; Hideo Fujiwara (ATS, 2007)

A DFT Method for Time Expansion Model at Register Transfer Level. - Hiroyuki Iwata; Tomokazu Yoneda; Hideo Fujiwara (DAC, 2007)

Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. - Tomokazu Yoneda; Masahiro Imanishi; Hideo Fujiwara (DATE, 2007)

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Hideo Fujiwara (ETS, 2007)

Efficient path delay test generation based on stuck-at test generation using checker circuitry. - Tsuyoshi Iwagaki; Satoshi Ohtake; Mineo Kaneko; Hideo Fujiwara (ICCAD, 2007)

Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. - Dan Zhao; Ronghua Huang; Tomokazu Yoneda; Hideo Fujiwara (ISCAS, 2007)

Fast and effective fault simulation for path delay faults based on selected testable paths. - Dong Xiang; Yang Zhao 001; Kaiwei Li; Hideo Fujiwara (ITC, 2007)

TAM Design and Optimization for Transparency-Based SoC Test. - Tomokazu Yoneda; Akiko Shuto; Hideyuki Ichihara; Tomoo Inoue; Hideo Fujiwara (VTS, 2007)

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. - Thomas Edison Yu; Tomokazu Yoneda; Danella Zhao; Hideo Fujiwara (VTS, 2007)

Functional Constraints vs. Test Compression in Scan-Based Delay Testing. - Ilia Polian; Hideo Fujiwara (J. Electron. Test., 2007)

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. - Masato Nakasato; Satoshi Ohtake; Kewal K. Saluja; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2007)

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on tauk-Notation. - Chia Yee Ooi; Thomas Clouqueur; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2007)

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. - Dong Xiang; Mingjing Chen; Hideo Fujiwara (IEEE Trans. Computers, 2007)

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. - Dong Xiang; Kaiwei Li; Jiaguang Sun; Hideo Fujiwara (IEEE Trans. Computers, 2007)

Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture. - Dong Xiang; Kaiwei Li; Hideo Fujiwara; Krishnaiyan Thulasiraman; Jiaguang Sun (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. - Yoshiyuki Nakamura; Thomas Clouqueur; Kewal K. Saluja; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Localized random access scan: Towards low area and routing overhead. - Yu Hu 001; Xiang Fu 007; Xiaoxin Fan; Hideo Fujiwara (ASP-DAC, 2008)

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. - Ryoichi Inoue; Toshinori Hosokawa; Hideo Fujiwara (ATS, 2008)

Untestable Fault Identification in Sequential Circuits Using Model-Checking. - Jaan Raik; Hideo Fujiwara; Raimund Ubar; Anna Krivenko (ATS, 2008)

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths. - Thomas Edison Yu; Tomokazu Yoneda; Satoshi Ohtake; Hideo Fujiwara (ATS, 2008)

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. - Tomokazu Yoneda; Hideo Fujiwara (DATE, 2008)

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Scheduling Power-Constrained Tests through the SoC Functional Bus. - Fawnizu Azmadi Hussin; Tomokazu Yoneda; Alex Orailoglu; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors. - Masato Nakasato; Michiko Inoue; Satoshi Ohtake; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint. - Tomokazu Yoneda; Kimihiko Masuda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints. - Thomas Edison Yu; Tomokazu Yoneda; Danella Zhao; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2008)

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. - Hideo Fujiwara; Hiroyuki Iwata; Tomokazu Yoneda; Chia Yee Ooi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST. - Dong Xiang; Yang Zhao 001; Krishnendu Chakrabarty; Hideo Fujiwara (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Fast false path identification based on functional unsensitizability using RTL information. - Yuki Yoshikawa; Satoshi Ohtake; Tomoo Inoue; Hideo Fujiwara (ASP-DAC, 2009)

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. - Thomas Edison Yu; Tomokazu Yoneda; Krishnendu Chakrabarty; Hideo Fujiwara (ASP-DAC, 2009)

Partial Scan Approach for Secret Information Protection. - Michiko Inoue; Tomokazu Yoneda; Muneo Hasegawa; Hideo Fujiwara (ETS, 2009)

A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. - Yuki Yoshikawa; Satoshi Ohtake; Tomoo Inoue; Hideo Fujiwara (VTS, 2009)

Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. - Michiko Inoue; Tsuyoshi Suzuki; Hideo Fujiwara (DISC, 2009)

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC. - Fawnizu Azmadi Hussin; Thomas Edison Yu; Tomokazu Yoneda; Hideo Fujiwara (APCCAS, 2010)

Secure and testable scan design using extended de Bruijn graphs. - Hideo Fujiwara; Marie Engelene J. Obien (ASP-DAC, 2010)

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. - Hiroshi Iwata; Satoshi Ohtake; Michiko Inoue; Hideo Fujiwara (Asian Test Symposium, 2010)

Seed Ordering and Selection for High Quality Delay Test. - Tomokazu Yoneda; Michiko Inoue; Akira Taketani; Hideo Fujiwara (Asian Test Symposium, 2010)

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. - Zhiqiang You; Jiedi Huang; Michiko Inoue; Jishun Kuang; Hideo Fujiwara (Asian Test Symposium, 2010)

SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan design. - Katsuya Fujiwara; Hideo Fujiwara; Marie Engelene J. Obien; Hideo Tamamoto (DDECS, 2010)

A synthesis method to propagate false path information from RTL to gate level. - Satoshi Ohtake; Hiroshi Iwata; Hideo Fujiwara (DDECS, 2010)

Enabling False Path Identification from RTL for Reducing Design and Test Futileness. - Hiroshi Iwata; Satoshi Ohtake; Hideo Fujiwara (DELTA, 2010)

Test pattern selection to optimize delay test quality with a limited size of test set. - Michiko Inoue; Akira Taketani; Tomokazu Yoneda; Hiroshi Iwata; Hideo Fujiwara (ETS, 2010)

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ETS, 2010)

Graph theoretic approach for scan cell reordering to minimize peak shift power. - Jaynarayan T. Tudu; Erik Larsson; Virendra Singh; Hideo Fujiwara (ACM Great Lakes Symposium on VLSI, 2010)

Aging test strategy and adaptive test scheduling for SoC failure prediction. - Hyunbean Yi; Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Seiji Kajihara; Hideo Fujiwara (IOLTS, 2010)

Constrained ATPG for functional RTL circuits using F-Scan. - Marie Engelene J. Obien; Satoshi Ohtake; Hideo Fujiwara (ITC, 2010)

RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. - Alodeep Sanyal; Krishnendu Chakrabarty; Mahmut Yilmaz; Hideo Fujiwara (ITC, 2010)

On Minimization of Test Application Time for RAS. - Raghavendra Adiga; Gandhi Arpit; Virendra Singh; Kewal K. Saluja; Hideo Fujiwara; Adit D. Singh (VLSI Design, 2010)

Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing. - Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Hideo Fujiwara (VTS, 2010)

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences. - Hongxia Fang; Krishnendu Chakrabarty; Hideo Fujiwara (J. Electron. Test., 2010)

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint. - Ryoichi Inoue; Toshinori Hosokawa; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2010)

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. - Hiroshi Iwata; Satoshi Ohtake; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2010)

Design and Optimization of Transparency-Based TAM for SoC Test. - Tomokazu Yoneda; Akiko Shuto; Hideyuki Ichihara; Tomoo Inoue; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2010)

Secure scan design using shift register equivalents against differential behavior attack. - Hideo Fujiwara; Katsuya Fujiwara; Hideo Tamamoto (ASP-DAC, 2011)

F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG. - Marie Engelene J. Obien; Satoshi Ohtake; Hideo Fujiwara (ETS, 2011)

Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. - Jaan Raik; Anna Rannaste; Maksim Jenihhin; Taavi Viilukas; Raimund Ubar; Hideo Fujiwara (ETS, 2011)

Temperature-Variation-Aware Test Pattern Optimization. - Tomokazu Yoneda; Makoto Nakao; Michiko Inoue; Yasuo Sato; Hideo Fujiwara (ETS, 2011)

Faster-than-at-speed test for increased test quality and in-field reliability. - Tomokazu Yoneda; Keigo Hori; Michiko Inoue; Hideo Fujiwara (ITC, 2011)

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. - Michiko Inoue; Tomokazu Yoneda; Muneo Hasegawa; Hideo Fujiwara (J. Electron. Test., 2011)

A New Design-for-Testability Method Based on Thru-Testability. - Chia Yee Ooi; Hideo Fujiwara (J. Electron. Test., 2011)

Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design. - Katsuya Fujiwara; Hideo Fujiwara; Hideo Tamamoto (IEICE Trans. Inf. Syst., 2011)

F-Scan: A DFT Method for Functional Scan at RTL. - Marie Engelene J. Obien; Satoshi Ohtake; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2011)

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. - Taavi Viilukas; Anton Karputkin; Jaan Raik; Maksim Jenihhin; Raimund Ubar; Hideo Fujiwara (J. Electron. Test., 2012)

Test Pattern Ordering and Selection for High Quality Test Set under Constraints. - Michiko Inoue; Akira Taketani; Tomokazu Yoneda; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2012)

A Failure Prediction Strategy for Transistor Aging. - Hyunbean Yi; Tomokazu Yoneda; Michiko Inoue; Yasuo Sato; Seiji Kajihara; Hideo Fujiwara (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Thermal-aware test scheduling for NOC-based 3D integrated circuits. - Dong Xiang; Gang Liu; Krishnendu Chakrabarty; Hideo Fujiwara (VLSI-SoC, 2013)

Generalized Feed Forward Shift Registers and Their Application to Secure Scan Design. - Katsuya Fujiwara; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2013)

Secure and Testable Scan Design Utilizing Shift Register Quasi-equivalents. - Katsuya Fujiwara; Hideo Fujiwara; Hideo Tamamoto (IPSJ Trans. Syst. LSI Des. Methodol., 2013)

A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation. - Tetsuya Masuda; Jun Nishimaki; Toshinori Hosokawa; Hideo Fujiwara (ATS, 2015)

One More Class of Sequential Circuits having Combinational Test Generation Complexity. - Debesh Kumar Das; Hideo Fujiwara (J. Electron. Test., 2015)

Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers. - Hideo Fujiwara; Katsuya Fujiwara (IEICE Trans. Inf. Syst., 2015)

A scheduling method for hierarchical testability based on test environment generation results. - Jun Nishimaki; Toshinori Hosokawa; Hideo Fujiwara (ETS, 2016)

A unified test and fault-tolerant multicast solution for network-on-chip designs. - Dong Xiang; Krishnendu Chakrabarty; Hideo Fujiwara (ITC, 2016)

Properties of Generalized Feedback Shift Registers for Secure Scan Design. - Hideo Fujiwara; Katsuya Fujiwara (IEICE Trans. Inf. Syst., 2016)

Realization of SR-Equivalents Using Generalized Shift Registers for Secure Scan Design. - Hideo Fujiwara; Katsuya Fujiwara (IEICE Trans. Inf. Syst., 2016)

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip. - Dong Xiang; Krishnendu Chakrabarty; Hideo Fujiwara (IEEE Trans. Computers, 2016)

Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents. - Hideo Fujiwara; Katsuya Fujiwara (IEICE Trans. Inf. Syst., 2017)

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing. - Dong Xiang; Krishnendu Chakrabarty; Hideo Fujiwara (ACM Trans. Design Autom. Electr. Syst., 2018)

A Test Generation Method Based on k-Cycle Testing for Finite State Machines. - Yuya Kinoshita; Toshinori Hosokawa; Hideo Fujiwara (IOLTS, 2019)

Universal Testing for Linear Feed-Forward/Feedback Shift Registers. - Hideo Fujiwara; Katsuya Fujiwara; Toshinori Hosokawa (IEICE Trans. Inf. Syst., 2020)