A hypercube design on wafer-scale integration. - Hideo Ito; Nobuyuki Suzuki (Syst. Comput. Jpn., 1991)

A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. - Hideo Ito (DFT, 1993)

Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. - Hideo Ito; Takashi Yagi (DFT, 1994)

Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons. - Hammadi Nait-Charif; Hideo Ito (J. Intell. Robotic Syst., 1998)

Testing the Logic Cells and Interconnect Resources for FPGAs. - Abderrahim Doumar; Hideo Ito (Asian Test Symposium, 1999)

Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. - Abderrahim Doumar; Satoshi Kaneko; Hideo Ito (DFT, 1999)

Design of an automatic testing for FPGAs. - Abderrahim Doumar; Toshiaki Ohmameuda; Hideo Ito (ETW, 1999)

Fault-Tolerant Routing Algorithms for Hypercube Networks. - Keiichi Kaneko; Hideo Ito (IPPS/SPDP, 1999)

Generalized Hierarchical Completely-Connected Networks. - Toshinori Takabatake; Keiichi Kaneko; Hideo Ito (ISPAN, 1999)

An Automatic Testing and Diagnosis for FPGAs. - Abderrahim Doumar; Hideo Ito (PRDC, 1999)

LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. - Mikio Yagi; Keiichi Kaneko; Hideo Ito (PRDC, 1999)

Testing approach within FPGA-based fault tolerant systems. - Abderrahim Doumar; Hideo Ito (Asian Test Symposium, 2000)

Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. - Abderrahim Doumar; Hideo Ito (DFT, 2000)

Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. - Masato Kitakami; Shunji Kubota; Hideo Ito (PRDC, 2001)

Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. - Toshinori Takabatake; Masato Kitakami; Hideo Ito (PRDC, 2001)

Optimal Seed Generation for Delay Fault Detection BIST. - Lihong Tong; Kazuki Suzuki; Hideo Ito (Asian Test Symposium, 2002)

A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. - Toshinori Takabatake; Masato Kitakami; Hideo Ito (IASTED PDCS, 2002)

Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. - Toshinori Takabatake; Masato Kitakami; Hideo Ito (PRDC, 2002)

Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. - Gang Zeng; Hideo Ito (DFT, 2003)

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. - Abderrahim Doumar; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. - Gang Zeng; Hideo Ito (DFT, 2004)

Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. - Manabu Sueishi; Masato Kitakami; Hideo Ito (PRDC, 2004)

Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. - Gang Zeng; Hideo Ito (VTS, 2004)

Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. - Gang Zeng; Hideo Ito (ICCD, 2005)

Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. - Kentaroh Katoh; Abderrahim Doumar; Hideo Ito (IOLTS, 2005)

Design of Defect Tolerant Wallace Multiplier. - Kazuteru Namba; Hideo Ito (PRDC, 2005)

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

Scan Design for Two-Pattern Test without Extra Latches. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. - Gang Zeng; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. - Gang Zeng; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. - Kazuteru Namba; Hideo Ito (ATS, 2006)

Concurrent core test for SOC using shared test set and scan chain disable. - Gang Zeng; Hideo Ito (DATE, 2006)

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. - Yoichi Sasaki 001; Kazuteru Namba; Hideo Ito (DFT, 2006)

Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. - Gang Zeng; Youhua Shi; Toshinori Takabatake; Masao Yanagisawa; Hideo Ito (DFT, 2006)

Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. - Kentaroh Katoh; Hideo Ito (ETS, 2006)

Proposal of Testable Multi-Context FPGA Architecture. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2006)

Redundant Design for Wallace Multiplier. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2006)

Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. - Gang Zeng; Hideo Ito (IEICE Trans. Inf. Syst., 2006)

Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. - Abderrahim Doumar; Kentaroh Katoh; Hideo Ito (DFT, 2007)

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. - Takashi Ikeda; Kazuteru Namba; Hideo Ito (DFT, 2007)

Low-Cost IP Core Test Using Tri-Template-Based Codes. - Gang Zeng; Hideo Ito (IEICE Trans. Inf. Syst., 2007)

Delay Fault Testability on Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (DFT, 2008)

Soft Error Hardened FF Capable of Detecting Wide Error Pulse. - Shuangyu Ruan; Kazuteru Namba; Hideo Ito (DFT, 2008)

Path Delay Fault Test Set for Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (PRDC, 2008)

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. - Yoichi Sasaki 001; Kazuteru Namba; Hideo Ito (J. Electron. Test., 2008)

A Checkpointing Method with Small Checkpoint Latency. - Masato Kitakami; Bochuan Cai; Hideo Ito (IEICE Trans. Inf. Syst., 2008)

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Connectivity of Generalized Hierarchical Completely-Connected Networks. - Toshinori Takabatake; Tomoki Nakamigawa; Hideo Ito (J. Interconnect. Networks, 2008)

A Delay Measurement Technique Using Signature Registers. - Kentaroh Katoh; Toru Tanabe; Haque Md Zahidul; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2009)

Testing of Switch Blocks in Three-Dimensional FPGA. - Takumi Hoshi; Kazuteru Namba; Hideo Ito (DFT, 2009)

Dependability Evaluation for Internet-Based Remote Systems. - Masato Kitakami; Akihiro Katada; Kazuteru Namba; Hideo Ito (PRDC, 2009)

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. - Kazuteru Namba; Yoshikazu Matsui; Hideo Ito (J. Electron. Test., 2009)

Design for Delay Fault Testability of 2-Rail Logic Circuits. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. - Shuangyu Ruan; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2010)

Soft Error Tolerant BILBO FF. - Kazuteru Namba; Hideo Ito (DFT, 2010)

Single Event Induced Double Node Upset Tolerant Latch. - Kazuteru Namba; Masatoshi Sakata; Hideo Ito (DFT, 2010)

Quantitative Evaluation of Integrity for Remote System Using the Internet. - Masato Kitakami; Hiroshi Konno; Kazuteru Namba; Hideo Ito (PRDC, 2010)

Chiba Scan Delay Fault Testing with Short Test Application Time. - Kazuteru Namba; Hideo Ito (J. Electron. Test., 2010)

Single-Event-Upset Tolerant RS Flip-Flop with Small Area. - Kazuteru Namba; Kengo Nakashima; Hideo Ito (IEICE Trans. Inf. Syst., 2010)

Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. - Kazuteru Namba; Takashi Ikeda; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Construction of BILBO FF with Soft-Error-Tolerant Capability. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2011)

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. - Kiyonori Matsumoto; Kazuteru Namba; Hideo Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (IEEE Trans. Computers, 2011)

Dual-edge-triggered FF with timing error detection capability. - Kazuteru Namba; Takashi Katagiri; Hideo Ito (DFT, 2012)

Improving small-delay fault coverage for on-chip delay measurement. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (DFT, 2012)

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. - Kazuteru Namba; Takashi Katagiri; Hideo Ito (J. Electron. Test., 2013)

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. - Kazuteru Namba; Nobuhide Takashina; Hideo Ito (IEICE Trans. Inf. Syst., 2013)

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2013)

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2014)

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2014)

High-Efficiency Milling of Steam Turbine Blade. - Xin Yuan; Takanori Yazawa; Hideo Ito; Tatsuki Otsubo; Yukio Maeda; Reiko Yamada (Int. J. Autom. Technol., 2016)