A Novel Image Sensor for Video Compression. - Kiyoharu Aizawa; Hideo Ohno; Takayuki Hamamoto; Mitsutoshi Hatori; Junichi Yamazaki (ICIP (3), 1994)

An ultralow power CMOS/SIMOX programmable counter LSI. - Yuichi Kado; Hideo Ohno; Mitsuru Harada; K. Deguchi; Toshiaki Tsuchiya (IEEE J. Solid State Circuits, 1997)

On sensor image compression. - Kiyoharu Aizawa; Hideo Ohno; Yuichiro Egi; Takayuki Hamamoto; Mitsutoshi Hatori; Hitoshi Maruyama; Junichi Yamazaki (IEEE Trans. Circuits Syst. Video Technol., 1997)

Electrical Magnetization Reversal in Ferromagnetic Semiconductors. - Fumihiro Matsukura; Daichi Chiba; Michihiko Yamanouchi; Hideo Ohno (ICMENS, 2004)

SPRAM (SPin-transfer torque RAM) design and its impact on digital systems. - Takayuki Kawahara; Riichiro Takemura; Hiromasa Takahashi; Hideo Ohno (ICECS, 2007)

2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (ISSCC, 2007)

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read. - Takayuki Kawahara; Riichiro Takemura; Katsuya Miura; Jun Hayakawa; Shoji Ikeda; Young Min Lee; Ryutaro Sasaki; Yasushi Goto; Kenchi Ito; Toshiyasu Meguro; Fumihiro Matsukura; Hiromasa Takahashi; et al. (IEEE J. Solid State Circuits, 2008)

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. - Shoun Matsunaga; Jun Hayakawa; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (DATE, 2009)

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits. - Fumitaka Iga; Masashi Kamiyanagi; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit. - Masashi Kamiyanagi; Fumitaka Iga; Shoji Ikeda; Katsuya Miura; Jun Hayakawa; Haruhiro Hasegawa; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEICE Trans. Electron., 2010)

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. - Riichiro Takemura; Takayuki Kawahara; Katsuya Miura; Hiroyuki Yamamoto; Jun Hayakawa; Nozomu Matsuzaki; Kazuo Ono; Michihiko Yamanouchi; Kenchi Ito; Hiromasa Takahashi; Shoji Ikeda; Haruhiro Hasegawa; et al. (IEEE J. Solid State Circuits, 2010)

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. - Shoun Matsunaga; Masanori Natsui; Shoji Ikeda; Katsuya Miura; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (ASP-DAC, 2012)

High-speed simulator including accurate MTJ models for spintronics integrated circuit design. - Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Hiroaki Honjo; Tadahiko Sugibayashi; Hiroki Koike; Takashi Ohsawa; Shunsuke Fukami; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (ISCAS, 2012)

A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. - Shoun Matsunaga; Sadahiko Miura; Hiroaki Honjou; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2012)

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keiichi Tokutome; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (VLSIC, 2012)

Spin-transfer torque RAM technology: Review and prospect. - Takayuki Kawahara; Kenchi Ito; Riichiro Takemura; Hideo Ohno (Microelectron. Reliab., 2012)

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (ISSCC, 2013)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. - Takashi Ohsawa; Hiroki Koike; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno; Tetsuo Endoh (IEEE J. Solid State Circuits, 2013)

Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. - Shunsuke Fukami; Hideo Sato; Michihiko Yamanouchi; Shoji Ikeda; Fumihiro Matsukura; Hideo Ohno (ASP-DAC, 2014)

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing. - Ryusuke Nebashi; Noboru Sakimura; Hiroaki Honjo; Ayuka Morioka; Yukihide Tsuji; Kunihiko Ishihara; Keiichi Tokutome; Sadahiko Miura; Shunsuke Fukami; Keizo Kinoshita; Takahiro Hanyu; Tetsuo Endoh; et al. (ISCAS, 2014)

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. - Noboru Sakimura; Yukihide Tsuji; Ryusuke Nebashi; Hiroaki Honjo; Ayuka Morioka; Kunihiko Ishihara; Keizo Kinoshita; Shunsuke Fukami; Sadahiko Miura; Naoki Kasai; Tetsuo Endoh; Hideo Ohno; et al. (ISSCC, 2014)

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. - Hooman Jarollahi; Naoya Onizawa; Vincent Gripon; Noboru Sakimura; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu; Warren J. Gross (IEEE J. Emerg. Sel. Topics Circuits Syst., 2014)

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. - Shoun Matsunaga; Akira Mochizuki; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. - Shoun Matsunaga; Akira Mochizuki; Noboru Sakimura; Ryusuke Nebashi; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. - Daisuke Suzuki; Noboru Sakimura; Masanori Natsui; Akira Mochizuki; Tadahiko Sugibayashi; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2014)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. - Masanori Natsui; Daisuke Suzuki; Noboru Sakimura; Ryusuke Nebashi; Yukihide Tsuji; Ayuka Morioka; Tadahiko Sugibayashi; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Shoji Ikeda; Tetsuo Endoh; et al. (IEEE J. Solid State Circuits, 2015)

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. - Masanori Natsui; Akira Tamakoshi; Akira Mochizuki; Hiroki Koike; Hideo Ohno; Tetsuo Endoh; Takahiro Hanyu (ISCAS, 2016)

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. - Tetsuo Endoh; Hiroki Koike; Shoji Ikeda; Takahiro Hanyu; Hideo Ohno (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. - Takahiro Hanyu; Tetsuo Endoh; Daisuke Suzuki; Hiroki Koike; Yitao Ma; Naoya Onizawa; Masanori Natsui; Shoji Ikeda; Hideo Ohno (Proc. IEEE, 2016)

Spintronics [Scanning the Issue]. - Hideo Ohno; Mark D. Stiles; Bernard Dieny (Proc. IEEE, 2016)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Integer factorization using stochastic magnetic tunnel junctions. - William A. Borders; Ahmed Zeeshan Pervaiz; Shunsuke Fukami; Kerem Yunus Çamsari; Hideo Ohno; Supriyo Datta (Nat., 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Double Free-Layer Magnetic Tunnel Junctions for Probabilistic Bits. - Kerem Yunus Çamsari; Mustafa Mert Torunbalci; William A. Borders; Hideo Ohno; Shunsuke Fukami (CoRR, 2020)

Hardware-aware in-situ Boltzmann machine learning using stochastic magnetic tunnel junctions. - Jan Kaiser; William A. Borders; Kerem Yunus Çamsari; Shunsuke Fukami; Hideo Ohno; Supriyo Datta (CoRR, 2021)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

A full-stack view of probabilistic computing with p-bits: devices, architectures and algorithms. - Shuvro Chowdhury; Andrea Grimaldi; Navid Anjum Aadit; Shaila Niazi; Masoud Mohseni; Shun Kanai; Hideo Ohno; Shunsuke Fukami; Luke Theogarajan; Giovanni Finocchio; Supriyo Datta; Kerem Yunus Çamsari (CoRR, 2023)

CMOS + stochastic nanomagnets: heterogeneous computers for probabilistic inference and learning. - Keito Kobayashi; Nihal Singh; Qixuan Cao; Kemal Selcuk; Tianrui Hu; Shaila Niazi; Navid Anjum Aadit; Shun Kanai; Hideo Ohno; Shunsuke Fukami; Kerem Yunus Çamsari (CoRR, 2023)

Double-Free-Layer Stochastic Magnetic Tunnel Junctions with Synthetic Antiferromagnets. - Kemal Selcuk; Shun Kanai; Rikuto Ota; Hideo Ohno; Shunsuke Fukami; Kerem Yunus Çamsari (CoRR, 2023)