A low-power 128-MHz VCO for monolithic PLL ICs. - Kazuo Kato; Takashi Sase; Hideo Sato; Ichiro Ikushima; Shin'ichi Kojima (IEEE J. Solid State Circuits, 1988)

A 300 MHz monolithic video current driver for high-resolution CRT applications. - Kazuo Kato; Hideo Sato; Yasuji Kamata; Kenkichi Yamashita; Seiichi Ueda (IEEE J. Solid State Circuits, 1989)

Personalizing the Appearance of Content Packages. - Alexander Kröner; Hideo Sato (LWA, 2004)

Development of a finger-mounted tactile sensor for surface irregularity detection. - Yoshihiro Tanaka; Hideo Sato; Hideo Fujimoto (IROS, 2007)

Real-time inspection of surface irregularity by finger-mounted tactile sensor. - Yoshihiro Tanaka; Hideo Sato; Hideo Fujimoto (RO-MAN, 2009)

Finger Vein Verification Technology for Mobile Apparatus. - Hideo Sato (SECRYPT, 2009)

A Study about Wireless Network Communication Performance at the Coastal Area for Underwater Monitoring Sensor Networks. - Kuniaki Kawabata; Takafumi Kobayashi; Fumiaki Takemura; Hideo Sato; Tsuyoshi Suzuki (IEICE Trans. Commun., 2010)

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Keizo Kinoshita; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (IEICE Electron. Express, 2013)

Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torque. - Shunsuke Fukami; Hideo Sato; Michihiko Yamanouchi; Shoji Ikeda; Fumihiro Matsukura; Hideo Ohno (ASP-DAC, 2014)

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. - Daisuke Suzuki; Masanori Natsui; Akira Mochizuki; Sadahiko Miura; Hiroaki Honjo; Hideo Sato; Shunsuke Fukami; Shoji Ikeda; Tetsuo Endoh; Hideo Ohno; Takahiro Hanyu (VLSIC, 2015)

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (ISSCC, 2019)

A novel memory test system with an electromagnet for STT-MRAM testing. - Ryo Tamura; N. Watanabe; Hiroki Koike; Hideo Sato; Shoji Ikeda; Tetsuo Endoh; Soshi Sato (NVMTS, 2019)

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. - Masanori Natsui; Daisuke Suzuki; Akira Tamakoshi; Toshinari Watanabe; Hiroaki Honjo; Hiroki Koike; Takashi Nasuno; Yitao Ma; Takaho Tanigawa; Yasuo Noguchi; Mitsuo Yasuhira; Hideo Sato; et al. (IEEE J. Solid State Circuits, 2019)

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (VLSI Circuits, 2020)

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. - Masanori Natsui; Akira Tamakoshi; Hiroaki Honjo; Toshinari Watanabe; Takashi Nasuno; Chaoliang Zhang; Takaho Tanigawa; Hirofumi Inoue; Masaaki Niwa; Toru Yoshiduka; Yasuo Noguchi; Mitsuo Yasuhira; et al. (IEEE J. Solid State Circuits, 2021)

Comprehensive study on prediction of endurance properties from breakdown voltage in high-reliable STT-MRAM. - Hideo Sato; H. M. Shin; H. Jung; S. W. Lee; H. Bae; H. Kwon; K. H. Ryu; W. C. Lim; Y. S. Han; J. H. Jeong; J. M. Lee; D. S. Kim; et al. (IRPS, 2023)