A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors. - Hitoshi Okamura; Hideo Toyoshima; Koichi Takeda; Takashi Oguri; Satoshi Nakamura; Masahide Takada; Kiyotaka Imai; Yasushi Kinoshita; Hiroshi Yoshida; Tom Yamazaki (IEEE J. Solid State Circuits, 1995)

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM. - Hideo Toyoshima; Shigeru Kuhara; Koichi Takeda 001; Kazuyuki Nakamura; Hiloshi Okamura; Masahide Takada; Hisamitsu Suzuki; Hiroshi Yoshida; Tohru Yamazaki (IEEE J. Solid State Circuits, 1996)

A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O. - Kazuyuki Nakamura; Koichi Takeda 001; Hideo Toyoshima; Kenji Noda; Hiroaki Ohkubo; Tetsuya Uchida; Toshiyuki Shimizu; Toshiro Itani; Ken Tokashiki; Koji Kishimoto (IEEE J. Solid State Circuits, 1997)

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. - Tohm Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Tom Tatsumi; Yukihiro Maejima; Hiromitsu Hada; Takemitsu Kunio (CICC, 2000)

An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. - Kenji Noda; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hiroyuki Kawamoto; Nobuyuki Ikezawa; Koichi Takeda 001; Yoshiharu Aimoto; Naoto Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Tadahiko Horiuchi (CICC, 2000)

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. - Koichi Takeda 001; Yoshiharu Aimoto; Noritsugu Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Kenji Noda; Koujirou Matsui; Shinya Itoh; Sadaaki Masuoka; Tadahiko Horiuchi; Atsushi Nakagawa; Kenju Shimogawa; et al. (IEEE J. Solid State Circuits, 2000)

FeRAM device and circuit technologies fully compatible with advanced CMOS. - Hideo Toyoshima; Sota Kobayashi; Junichi Yamada; Tohru Miwa; Hiroki Koike; Hidenori Takeuchi; Hidemitsu Mori; Naoki Kasai; Yukihiko Maejima; Nobuhira Tanabe; Toru Tatsumi; Hiromitsu Hada (CICC, 2001)

NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. - Tohru Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiko Maejima; Hiromitsu Hada; Takemitsu Kunio (IEEE J. Solid State Circuits, 2001)

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. - Junichi Yamada; Tohru Miwa; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiko Maejima; Hiromitsu Hada; Hidemitsu Mori; Seiichi Takahashi; Hidenori Takeuchi; et al. (IEEE J. Solid State Circuits, 2002)