High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System. - Hideo Wada; Koichi Ishii; Shigeko Yazawa; Shun Kawabe (ICPP (1), 1988)

High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system. - Hideo Wada; K. Ishil; Masakazu Fukagawa; H. Murayama; Shun Kawabe (ICS, 1988)

High-speed storage control schemes of HITACHI supercomputer S-820 system. - Hideo Wada; Tadaaki Isobe; Masao Furukawa; Shun Kawabe (ICS, 1989)

An Overview of the HITACHI S-820 Supercomputer System. - Michihiro Hirai; Shun Kawabe; Hideo Wada (Supercomputer, 1989)

A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. - Hiroshi Nakamura; Taisuke Boku; Hideo Wada; Hiromitsu Imori; Ikuo Nakata; Yasuhiro Inagami; Kisaburo Nakazawa; Yoshiyuki Yamashita (International Conference on Supercomputing, 1993)

Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System. - Hiroaki Fujii; Yoshiko Yasuda; Hideya Akashi; Yasuhiro Inagami; Makoto Koga; Osamu Ishihara; Masamori Kashiyama; Hideo Wada; Tsutomu Sumimoto (IPPS, 1997)

Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201. - Yoshiko Yasuda; Hiroaki Fujii; Hideya Akashi; Yasuhiro Inagami; Teruo Tanaka; Junji Nakagoshi; Hideo Wada; Tsutomu Sumimoto (IPPS, 1997)

On Self-dual Codes over Z16. - Kiyoshi Nagata; Fidel R. Nemenzo; Hideo Wada (AAECC, 2009)

The number of self-dual codes over Zp3{Z_{p^3}}. - Kiyoshi Nagata; Fidel R. Nemenzo; Hideo Wada (Des. Codes Cryptogr., 2009)

Mass formula and structure of self-dual codes over Z2s. - Kiyoshi Nagata; Fidel R. Nemenzo; Hideo Wada (Des. Codes Cryptogr., 2013)