A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors. - Masakazu Yagi; Hideo Yamasaki; Tadashi Shibata (NIPS, 2003)

A real-time VLSI median filter employing two-dimensional bit-propagating architecture. - Hideo Yamasaki; Tadashi Shibata (ISCAS (2), 2004)

A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. - Hideo Yamasaki; Tadashi Shibata (ESSCIRC, 2005)

A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture. - Hideo Yamasaki; Tadashi Shibata (IEEE J. Solid State Circuits, 2007)