LSSD Compatible and Concurrently Testable Ram. - Hideshi Maeno; Koji Nii; S. Sakayanagi; S. Kato (ITC, 1992)

A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. - Koji Nii; Hideshi Maeno; Tokuya Osawa; Shuhei Iwade; Shinpei Kayano; Hiroshi Shibata (IEEE J. Solid State Circuits, 1995)