Spatial computing architecture using randomness of memory cell stability under voltage control. - Chihiro Yoshimura; Masanao Yamaoka; Hidetaka Aoki; Hiroyuki Mizuno (ECCTD, 2013)

An Accelerator Chip for Ground-State Searches of the Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (CANDAR, 2015)

24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (ISSCC, 2015)

Accelerator Chip for Ground-state Searches of Ising Model with Asynchronous Random Pulse Distribution. - Masato Hayashi; Masanao Yamaoka; Chihiro Yoshimura; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (Int. J. Netw. Comput., 2016)

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing. - Masanao Yamaoka; Chihiro Yoshimura; Masato Hayashi; Takuya Okuyama; Hidetaka Aoki; Hiroyuki Mizuno (IEEE J. Solid State Circuits, 2016)

An empirical study on performance optimization at district cooling plant of Universiti Teknologi PETRONAS. - Xiaoming Zhang; Hidetaka Aoki; Akiko Sato; Mohd Amin Abd Majid (APSIPA, 2017)