Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima; Y. Hayasaka (ITC, 1986)

Twisted bit-line architectures for multi-megabit DRAMs. - Hideto Hidaka; Kazuyasu Fujishima; Yoshio Matsuda; Mikio Asakura; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1989)

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1989)

The cache DRAM architecture: a DRAM with an on-chip cache memory. - Hideto Hidaka; Yoshio Matsuda; Mikio Asakura; Kazuyasu Fujishima (IEEE Micro, 1990)

A circuit design of intelligent cache DRAM with automatic write-back capability. - Kazutami Arimoto; Mikio Asakura; Hideto Hidaka; Yoshio Matsuda; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1991)

A divided/shared bit-line sensing scheme for ULSI DRAM cores. - Hideto Hidaka; Yoshio Matsuda; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1991)

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsunori Suma; Kazuyasu Fujishima (ITC, 1992)

Cell-plate line connecting complementary bit-line (C3) architecture for battery-operated DRAMs. - Mikio Asakura; Kazutami Arimoto; Hideto Hidaka; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A dual-mode sensing scheme of capacitor-coupled EEPROM cell. - Masanori Hayashikoshi; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. - Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsuhiro Suma; Kazuyasu Fujishima (IEEE Des. Test Comput., 1993)

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. - Tsukasa Ooishi; Mikio Asakura; Shigeki Tomishima; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1994)

An experimental 256-Mb DRAM with boosted sense-ground scheme. - Mikio Asakura; Tsukasa Ooishi; Masaki Tsukude; Shigeki Tomishima; Takahisa Eimori; Hideto Hidaka; Yoshikazu Ohno; Kazutani Arimoto; Kazuyasu Fujishima; Tadashi Nishimura; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 1994)

An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology. - Katsuhiro Suma; Takahiro Tsuruda; Hideto Hidaka; Takahisa Eimori; Toshiyuki Oashi; Yasuo Yamaguchi; Toshiaki Iwamatsu; Masakazu Hirose; Fukashi Morishita; Kazutarni Arimoto; Kazuyasu Fujishima; Yasuo Inoue; et al. (IEEE J. Solid State Circuits, 1994)

An automatic temperature compensation of internal sense ground for subquarter micron DRAM's. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mho Asakura; Kenichi Yasuda; Kiyohiro Furutani; Hideto Hidaka; Hiroshi Miyamoto; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1995)

A mixed-mode voltage down converter with impedance adjustment circuitry for low-voltage high-frequency memories. - Tsukasa Ooishi; Yuichiro Komiya; Kei Hamade; Mikio Asakura; Kenichi Yasuda; Kiyohiro Furutani; Tetsuo Kato; Hideto Hidaka; Hideyuki Ozaki (IEEE J. Solid State Circuits, 1996)

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. - Hitoshi Tanaka; Masakazu Aoki; Takeshi Sakata; Shin'ichiro Kimura; Narumi Sakashita; Hideto Hidaka; Tadashi Tachibana; Katsutaka Kimura (IEEE J. Solid State Circuits, 1999)

A built-in self-repair analyzer (CRESTA) for embedded DRAMs. - Tomoya Kawagoe; Jun Ohtani; Mitsutaka Niiro; Tukasa Ooishi; Mitsuhiro Hamada; Hideto Hidaka (ITC, 2000)

A shared built-in self-repair analysis for multiple embedded memories. - Jun Ohtani; Tukasa Ooishi; Tomoya Kawagoe; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka (CICC, 2001)

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. - Shigeki Tomishima; Hiroaki Tanizaki; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka; T. Tada; Kenji Gamo (ITC, 2002)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

Non-Volatile Memories. - Hideto Hidaka; Yair Sofer (ISSCC, 2007)

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. - Donhee Ham; Hideto Hidaka; Ron Ho; Ram K. Krishnamurthy (IEEE J. Solid State Circuits, 2009)

Silicon 3D-integration technology and systems. - Pascal Urard; Ken Takeuchi; Kerry Bernstein; Hideto Hidaka; Michael Phan; Joo-Sun Choi; Bob Payne; Vladimir Stojanovic; Kees van Berkel 001; Takayasu Sakurai (ISSCC, 2010)

Session 1 overview: Plenary session. - Anantha P. Chandrakasan; Hideto Hidaka (ISSCC, 2012)

40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data. - Takashi Kono; Takashi Ito; Tamaki Tsuruda; Takayuki Nishiyama; Tsutomu Nagasawa; Tomoya Ogawa; Yoshiyuki Kawashima; Hideto Hidaka; Tadaaki Yamauchi (ISSCC, 2013)

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C. - Takashi Kono; Takashi Ito; Tamaki Tsuruda; Takayuki Nishiyama; Tsutomu Nagasawa; Tomoya Ogawa; Yoshiyuki Kawashima; Hideto Hidaka; Tadaaki Yamauchi (IEEE J. Solid State Circuits, 2014)

How future mobility meets IT: Cyber-physical system designs revisit semiconductor technology. - Hideto Hidaka (A-SSCC, 2015)

7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C. - Yasuhiko Taito; Masaya Nakano; Hiromi Okimoto; Daisuke Okada; Takashi Ito; Takashi Kono; Kenji Noguchi; Hideto Hidaka; Tadaaki Yamauchi (ISSCC, 2015)

7.6 A 90nm embedded 1T-MONOS flash macro for automotive applications with 0.07mJ/8kB rewrite energy and endurance over 100M cycles under Tj of 175°C. - Hidenori Mitani; Ken Matsubara; Hiroshi Yoshida; Takashi Hashimoto; Hideaki Yamakoshi; Shinichiro Abe; Takashi Kono; Yasuhiko Taito; Takashi Ito; Takashi Krafuji; Kenji Noguchi; Hideto Hidaka; et al. (ISSCC, 2016)

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C. - Yasuhiko Taito; Takashi Kono; Masaya Nakano; Tomoya Saito; Takashi Ito; Kenji Noguchi; Hideto Hidaka; Tadaaki Yamauchi (IEEE J. Solid State Circuits, 2016)

Introduction. - Hideto Hidaka (Embedded Flash Memory for Embedded Systems, 2018)

Applications and Technology Trend in Embedded Flash Memory. - Hideto Hidaka (Embedded Flash Memory for Embedded Systems, 2018)

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. - Masanori Hayashikoshi; Hiroaki Tanizaki; Yasumitsu Murai; Takaharu Tsuji; Kiyoshi Kawabata; Koji Nii; Hideyuki Noda; Hiroyuki Kondo; Yoshio Matsuda; Hideto Hidaka (IEICE Trans. Electron., 2019)

Foreword. - Hideto Hidaka (IEICE Trans. Electron., 2019)

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age. - Takashi Kono; Yasuhiko Taito; Hideto Hidaka (IEICE Trans. Electron., 2020)