System design of a special-purpose computer for LSI design rule checking. - Keikichi Tamaru; Hidetoshi Onodera (Syst. Comput. Jpn., 1987)

A cyclic A/D converter that does not require ratio-matched components. - Hidetoshi Onodera; Tetsuo Tateishi; Keikichi Tamaru (IEEE J. Solid State Circuits, 1988)

An efficient algorithm for layout compaction problem with symmetry constraints. - R. Okuda; Takashi Sato 001; Hidetoshi Onodera; K. Tamariu (ICCAD, 1989)

Operational-amplifier compilation with performance optimization. - Hidetoshi Onodera; Hiroyuki Kanbara; Keikichi Tamaru (IEEE J. Solid State Circuits, 1990)

Branch-and-Bound Placement for Building Block Layout. - Hidetoshi Onodera; Yo Taniguchi; Keikichi Tamaru (DAC, 1991)

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. - Vasily G. Moshnyaga; Hiroshi Mori; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1993)

A model-adaptable MOSFET parameter extraction system. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1995)

An iterative gate sizing approach with accurate delay evaluation. - Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1995)

Timing and Power Optimization by Gate Sizing Considering False Paths. - Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru (Great Lakes Symposium on VLSI, 1996)

A functional memory type parallel processor for vector quantization. - Kazutoshi Kobayashi; Masayoshi Kinoshita; Masahiro Takeuchi; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1997)

A current mode cyclic A/D converter with a 0.8 μm CMOS process. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1997)

Proposal of a timing model for CMOS logic gates driving a CRC load. - Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1998)

A power optimization method considering glitch reduction by gate sizing. - Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru (ISLPED, 1998)

Model-adaptable MOSFET parameter-extraction method using an intermediate model. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. - Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru (DAC, 1999)

A method for linking process-level variability to system performances. - Tomohiro Fujita; Ken-ichi Okada 001; Hiroaki Fujita; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 2000)

Statistical delay calculation with vector synthesis model. - Tomohiro Fujita; Hidetoshi Onodera (ISCAS, 2000)

Statistical modeling of device characteristics with systematic fluctuation. - Kenichi Okada 001; Hidetoshi Onodera (ISCAS, 2000)

A performance optimization method by gate sizing using statistical static timing analysis. - Masanori Hashimoto; Hidetoshi Onodera (ISPD, 2000)

Post-layout transistor sizing for power reduction in cell-based design. - Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2001)

A vector-pipeline DSP for low-rate videophones. - Kazutoshi Kobayashi; Makoto Eguchi; Takuya Iwahashi; Takehide Shibayama; Xiang Li; Kousuke Takai; Hidetoshi Onodera (ASP-DAC, 2001)

Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. - Hidetoshi Onodera; Andrew B. Kahng; Wayne Wei-Ming Dai; Sani R. Nassif; Juho Kim; Akira Tanabe; Toshihiro Hattori (ASP-DAC, 2001)

A dynamically phase adjusting PLL with a variable delay. - Takeo Yasuda; Hiroaki Fujita; Hidetoshi Onodera (ASP-DAC, 2001)

ST: PERL package for simulation and test environment. - Kazutoshi Kobayashi; Hidetoshi Onodera (ISCAS (5), 2001)

Measurement results of on-chip IR-drop. - Kazutoshi Kobayashi; Junji Yamaguchi; Hidetoshi Onodera (CICC, 2002)

Crosstalk noise optimization by post-layout transistor sizing. - Masanori Hashimoto; Masao Takahashi; Hidetoshi Onodera (ISPD, 2002)

Experimental Study on Cell-Base High-Performance Datapath Design. - Masanori Hashimoto; Yashiteru Hayashi; Hidetoshi Onodera (IWLS, 2002)

Increase in Delay Uncertainty by Performance Optimization. - Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies. - Masanori Hashimoto; Kazunori Fujimori; Hidetoshi Onodera (ASP-DAC, 2003)

A statistical gate delay model for intra-chip and inter-chip variabilities. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ASP-DAC, 2003)

A Statistical Gate-Delay Model Considering Intra-Gate Variability. - Ken-ichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ICCAD, 2003)

Statistical modeling of gate-delay variation with consideration of intra-gate variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (ISCAS (5), 2003)

Capturing crosstalk-induced waveform for accurate static timing analysis. - Masanori Hashimoto; Yuji Yamada; Hidetoshi Onodera (ISPD, 2003)

Experimental Study on Cell-Base High-Performance Datapath Design. - Masanori Hashimoto; Yoshiteru Hayashi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Crosstalk Noise Estimation for Generic RC Trees. - Masanori Hashimoto; Masao Takahashi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence. - Kenichi Okada 001; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Statistical Gate-Delay Modeling with Intra-Gate Variability. - Kenichi Okada 001; Kento Yamaoka; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Representative Frequency for Interconnect R(f)L(f)C Extraction. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process. - Takahito Miyazaki; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2004)

An SoC architecture and its design methodology using unifunctional heterogeneous processor array. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2004)

Performance limitation of on-chip global interconnects for high-speed signaling. - Akira Tsuchiya; Yuuya Gotoh; Masanori Hashimoto; Hidetoshi Onodera (CICC, 2004)

Modelling and optimization of on-chip spiral inductor in S-parameter domain. - Ken-ichi Okada 001; Hiroaki Hoshino; Hidetoshi Onodera (ISCAS (5), 2004)

RTL/ISS co-modeling methodology for embedded processor using SystemC. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ISCAS (5), 2004)

Automatic Generation of Standard Cell Library in VDSM Technologies. - Masanori Hashimoto; Kazunori Fujimori; Hidetoshi Onodera (ISQED, 2004)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification. - Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Inf. Syst., 2004)

Equivalent waveform propagation for static timing analysis. - Masanori Hashimoto; Yuji Yamada; Hidetoshi Onodera (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. - Kazutoshi Kobayashi; Masao Aramoto; Yoichi Yuyama; Akihiko Higuchi; Hidetoshi Onodera (ASP-DAC, 2005)

Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. - Takashi Sato 001; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2005)

Design and measurement of 6.4 Gbps 8: 1 multiplexer in 0.18µm CMOS process. - Akinori Shinmyo; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2005)

Return path selection for loop RL extraction. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2005)

A yield and speed enhancement scheme under within-die variations on 90nm LUT array. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (CICC, 2005)

Substrate and phase noise characterization. - Steffen Rochel; Hidetoshi Onodera (CICC, 2005)

Design guideline for resistive termination of on-chip high-speed interconnects. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (CICC, 2005)

Statistical Analysis of Clock Skew Variation in H-Tree Structure. - Masanori Hashimoto; Tomonori Yamamoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. - Kazutoshi Kobayashi; Masao Aramoto; Hidetoshi Onodera (IEICE Trans. Electron., 2005)

A Performance Prediction of Clock Generation PLLs: A Ring Oscillator Based PLL and an LC Oscillator Based PLL. - Takahito Miyazaki; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Electron., 2005)

Effects of On-Chip Inductance on Power Distribution Grid. - Atsushi Muramatsu; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Successive Pad Assignment for Minimizing Supply Voltage Drop. - Takashi Sato 001; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2006)

Interconnect RL extraction at a single representative frequency. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (ASP-DAC, 2006)

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. - Kazutoshi Kobayashi; Manabu Kotani; Kazuya Katsuki; Y. Takatsukasa; K. Ogata; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2006)

Consideration of Transition-Time Variability in Statistical Timing Analysis. - Takeshi Kouno; Hidetoshi Onodera (SoCC, 2006)

A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design. - Masanao Yamaoka; Hidetoshi Onodera (SoCC, 2006)

Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. - Toshiki Kanamoto; Tatsuhiko Ikeda; Akira Tsuchiya; Hidetoshi Onodera; Masanori Hashimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era. - Kazutoshi Kobayashi; Akihiko Higuchi; Hidetoshi Onodera (IEICE Trans. Electron., 2006)

Special Section on VLSI Design and CAD Algorithms. - Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Variability: Modeling and Its Impact on Design. - Hidetoshi Onodera (IEICE Trans. Electron., 2006)

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. - Yoichi Yuyama; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2006)

A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. - Takeshi Kuboki; Akira Tsuchiya; Hidetoshi Onodera (ASP-DAC, 2007)

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. - Yuuri Sugihara; Manabu Kotani; Kazuya Katsuki; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2007)

Worst-case delay analysis considering the variability of transistors and interconnects. - Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (ISPD, 2007)

Timing Analysis Considering Spatial Power/Ground Level Variation. - Masanori Hashimoto; Junji Yamaguchi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. - Kazutoshi Kobayashi; Kazuya Katsuki; Manabu Kotani; Yuuri Sugihara; Yohei Kume; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. - Takeshi Kuboki; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

Manufacturability-Aware Design of Standard Cells. - Hirokazu Muta; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. - Akira Tsuchiya; Masanori Hashimoto; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. - Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2008)

Session 2 - Statistical modeling. - Hidetoshi Onodera; Hong-Ha Vuong (CICC, 2008)

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPGA, 2008)

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. - Kazutoshi Kobayashi; Yohei Kume; Cam Lai Ngo; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2008)

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPL, 2008)

Timing Analysis Considering Temporal Supply Voltage Fluctuation. - Masanori Hashimoto; Junji Yamaguchi; Takashi Sato 001; Hidetoshi Onodera (IEICE Trans. Inf. Syst., 2008)

Analytical Model of Static Noise Margin in CMOS SRAM for Variation Consideration. - Hirofumi Shinohara; Koji Nii; Hidetoshi Onodera (IEICE Trans. Electron., 2008)

Welcome to TSLDM - A New Open-Access Online Journal from IPSJ. - Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. - Haruhiko Terada; Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Dependable VLSI: device, design and architecture: how should they cooperate? - Shuichi Sakai; Hidetoshi Onodera; Hiroto Yasuura; James C. Hoe (ASP-DAC, 2009)

Modeling of passive elements and reliability. - Gennady Gildenblat; Hidetoshi Onodera (CICC, 2009)

Erect of regularity-enhanced layout on printability and circuit performance of standard cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (ISQED, 2009)

Statistical Gate Delay Model for Multiple Input Switching. - Takayuki Fukuoka; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (CICC, 2010)

Warning Prediction Sequential for Transient Error Prevention. - Bishnu Prasad Das; Hidetoshi Onodera (DFT, 2010)

A design procedure of predictive RF MOSFET model for compatibility with ITRS. - SinNyoung Kim; Akira Tsuchiya; Hidetoshi Onodera (SoCC, 2010)

Variation-tolerant design of D-flipflops. - Hiroki Sunagawa; Hidetoshi Onodera (SoCC, 2010)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2010)

Message from the Editor-in-Chief. - Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. - Jun Furuta; Chikara Hamanaka; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2011)

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. - Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (A-SSCC, 2011)

An area effective forward/reverse body bias generator for within-die variability compensation. - Norihiro Kamae; Akira Tsuchiya; Hidetoshi Onodera (A-SSCC, 2011)

Dependable VLSI Program in Japan: Program Overview and the Current Status of Dependable VLSI Platform Project. - Hidetoshi Onodera (Asian Test Symposium, 2011)

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. - Shigekazu Miyawaki; Makoto Nakamura; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ISOCC, 2011)

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. - Akira Tsuchiya; Takeshi Kuboki; Yusuke Ohtomo; Keiji Kishine; Shigekazu Miyawaki; Makoto Nakamura; Hidetoshi Onodera (ISOCC, 2011)

Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. - Kyosuke Ito; Takashi Matsumoto; Shinichi Nishizawa; Hiroki Sunagawa; Kazutoshi Kobayashi; Hidetoshi Onodera (ISQED, 2011)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. - Chikara Hamanaka; Ryosuke Yamamoto; Jun Furuta; Kanto Kubota; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2012)

On-Chip Detection of Process Shift and Process Spread for Silicon Debugging and Model-Hardware Correlation. - Islam A. K. M. Mahfuzul; Hidetoshi Onodera (Asian Test Symposium, 2012)

Modeling & design for variability and reliability. - Trent McConaghy; Hidetoshi Onodera (CICC, 2012)

A flexible structure of standard cell and its optimization method for near-threshold voltage operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (ICCD, 2012)

A Standard Cell Optimization Method for Near-Threshold Voltage Operations. - Masahiro Kondo; Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2012)

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Area-efficient reconfigurable-array-based oscillator for standard cell characterisation. - Bishnu Prasad Das; Hidetoshi Onodera (IET Circuits Devices Syst., 2012)

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2013)

Dependable VLSI Platform using Robust Fabrics. - Hidetoshi Onodera (ASP-DAC, 2013)

AMS verification in advanced technologies. - Hidetoshi Onodera; Yu Kevin Cao (CICC, 2013)

Perturbation-immune radiation-hardened PLL with a switchable DMR structure. - SinNyoung Kim; Akira Tsuchiya; Hidetoshi Onodera (IOLTS, 2013)

Analysis and comparison of XOR cell structures for low voltage circuit design. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2013)

On-Chip Detection of Process Shift and Process Spread for Post-Silicon Diagnosis and Model-Hardware Correlation. - Islam A. K. M. Mahfuzul; Hidetoshi Onodera (IEICE Trans. Inf. Syst., 2013)

Standard Cell Structure with Flexible P/N Well Boundaries for Near-Threshold Voltage Operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. - Kuiyuan Zhang; Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2013)

A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. - Norihiro Kamae; Islam A. K. M. Mahfuzul; Akira Tsuchiya; Hidetoshi Onodera (A-SSCC, 2014)

Variability and Soft-Error Resilience in Dependable VLSI Platform. - Yukio Mitsuyama; Hidetoshi Onodera (ATS, 2014)

Impact of random telegraph noise on CMOS logic circuit reliability. - Takashi Matsumoto; Kazutoshi Kobayashi; Hidetoshi Onodera (CICC, 2014)

Modeling of advanced devices. - Colin McAndrew; Hidetoshi Onodera (CICC, 2014)

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. - Keiji Kishine; Hiroshi Inoue; Hiromi Inaba; Makoto Nakamura; Akira Tsuchiya; Hidetoshi Onodera; Hiroaki Katsurai (ISCAS, 2014)

Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model. - Tomohiro Fujita; SinNyoung Kim; Hidetoshi Onodera (ISQED, 2014)

Variation-aware Flip-Flop energy optimization for ultra low voltage operation. - Tatsuya Kamakari; Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2014)

Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2014)

Characterization and compensation of performance variability using on-chip monitors. - Islam A. K. M. Mahfuzul; Hidetoshi Onodera (VLSI-DAT, 2014)

A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation. - Norihiro Kamae; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop. - SinNyoung Kim; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure. - SinNyoung Kim; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Electron., 2014)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator. - Bishnu Prasad Das; Hidetoshi Onodera (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs. - Bishnu Prasad Das; Hidetoshi Onodera (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. - Masanori Hashimoto; Dawood Alnajiar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera (ASP-DAC, 2015)

Microarchitectural-level statistical timing models for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2015)

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. - Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka; Akira Tsuchiya; Hidetoshi Onodera; Shunji Kimura (A-SSCC, 2015)

Session 23 - Modeling emerging devices. - Chenjie Gu; Hidetoshi Onodera (CICC, 2015)

Energy reduction by built-in body biasing with single supply voltage operation. - Norihiro Kamae; Islam A. K. M. Mahfuzul; Akira Tsuchiya; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2015)

An energy-efficient on-chip memory structure for variability-aware near-threshold operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2015)

An impact of process variation on supply voltage dependence of logic path delay variation. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (VLSI-DAT, 2015)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2015)

A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage. - Norihiro Kamae; Akira Tsuchiya; Hidetoshi Onodera (IEICE Trans. Electron., 2015)

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell. - Shinichi Nishizawa; Tohru Ishihara; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring. - Islam A. K. M. Mahfuzul; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEEE J. Solid State Circuits, 2015)

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. - Keiji Kishine; Hiromi Inaba; Hiroshi Inoue; Makoto Nakamura; Akira Tsuchiya; Hiroaki Katsurai; Hidetoshi Onodera (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ASP-DAC, 2016)

On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations. - Islam A. K. M. Mahfuzul; Hidetoshi Onodera (ASP-DAC, 2016)

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. - Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Hiroyuki Ochi; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Kazutoshi Wakabayashi; Hidetoshi Onodera; Yukio Mitsuyama; Masanori Hashimoto (FPL, 2016)

Variability- and correlation-aware logical effort for near-threshold circuit design. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (ISQED, 2016)

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2016)

Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing. - Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2016)

2016 ASP-DAC. - Hidetoshi Onodera (IEEE Des. Test, 2016)

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation. - Tatsuya Kamakari; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. - Akitaka Hiratsuka; Akira Tsuchiya; Hidetoshi Onodera (MWSCAS, 2017)

Effect of supply voltage on random telegraph noise of transistors under switching condition. - Islam A. K. M. Mahfuzul; Hidetoshi Onodera (PATMOS, 2017)

Pin accessibility evaluating model for improving routability of VLSI designs. - Hong-Yan Su; Shinichi Nishizawa; Yan-Shiun Wu; Jun Shiomi; Yih-Lang Li; Hidetoshi Onodera (SoCC, 2017)

On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator. - Tadashi Kishimoto; Tohru Ishihara; Hidetoshi Onodera (VLSI-DAT, 2017)

A Minimum Energy Point Tracking Algorithm Based on Dynamic Voltage Scaling and Adaptive Body Biasing. - Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. - Akitaka Hiratsuka; Akira Tsuchiya; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (A-SSCC, 2018)

PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process. - A. K. M. Mahfuzul Islam; Hidetoshi Onodera (ICCAD, 2018)

Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics. - Takumi Egawa; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Shota Kita; Kengo Nozaki; Kenta Takata; Masaya Notomi (ICRC, 2018)

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2018)

Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation. - Yosuke Okamura; Tohru Ishihara; Hidetoshi Onodera (IOLTS, 2018)

Process variation aware D-Flip-Flop design using regression analysis. - Shinichi Nishizawa; Hidetoshi Onodera (ISQED, 2018)

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. - Toshiyuki Inoue; Ryosuke Noguchi; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (MWSCAS, 2018)

Worst-Case Performance Analysis Under Random Telegraph Noise Induced Threshold Voltage Variability. - A. K. M. Mahfuzul Islam; Hidetoshi Onodera (PATMOS, 2018)

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (PATMOS, 2018)

Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization. - Tatsuhiro Higuchi; Tohru Ishihara; Hidetoshi Onodera (SoCC, 2018)

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. - Hiroki Hihara; Akira Iwasaki; Masanori Hashimoto; Hiroyuki Ochi; Yukio Mitsuyama; Hidetoshi Onodera; Hiroyuki Kanbara; Kazutoshi Wakabayashi; Tadahiko Sugibayashi; Takashi Takenaka; Hiromitsu Hada; Munehiro Tada; et al. (IEEE Embed. Syst. Lett., 2018)

Design Methodology for Variation Tolerant D-Flip-Flop Using Regression Analysis. - Shinichi Nishizawa; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Minimum Energy Point Tracking with All-Digital On-Chip Sensors. - Jun Shiomi; Shu Hokimoto; Tohru Ishihara; Hidetoshi Onodera (J. Low Power Electron., 2018)

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars. - Hiroyuki Ochi; Kosei Yamaguchi; Tetsuaki Fujimoto; Junshi Hotate; Takashi Kishimoto; Toshiki Higashi; Takashi Imagawa; Ryutaro Doi; Munehiro Tada; Tadahiko Sugibayashi; Wataru Takahashi 002; Kazutoshi Wakabayashi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2018)

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ASP-DAC, 2019)

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (DAC, 2019)

Analysis of Random Telegraph Noise (RTN) at Near-Threshold Operation by Measuring 154k Ring Oscillators. - A. K. M. Mahfuzul Islam; Ryota Shimizu; Hidetoshi Onodera (IRPS, 2019)

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (SoCC, 2019)

A Design Method of a Cell-Based Amplifier for Body Bias Generation. - Takuya Koyanagi; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. - Akira Tsuchiya; Akitaka Hiratsuka; Toshiyuki Inoue; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. - Hongjie Xu; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera (Integr., 2019)

Circuit Techniques for Device-Circuit Interaction toward Minimum Energy Operation. - A. K. M. Mahfuzul Islam; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias. - Kentaro Nagai; Jun Shiomi; Hidetoshi Onodera (APCCAS, 2020)

On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (ACM Great Lakes Symposium on VLSI, 2020)

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hidetoshi Onodera (ICCAD, 2020)

An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics. - Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ICRC, 2020)

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications. - Masanori Hashimoto; Xu Bai; Naoki Banno; Munehiro Tada; Toshitsugu Sakamoto; Jaehoon Yu; Ryutaro Doi; Yusuke Araki; Hidetoshi Onodera; Takashi Imagawa; Hiroyuki Ochi; Kazutoshi Wakabayashi; et al. (ISSCC, 2020)

A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (ISVLSI, 2020)

Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (SoCC, 2020)

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (IEICE Trans. Electron., 2020)

Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics. - Jun Shiomi; Shuya Kotsugi; Boyu Dong; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (DAC, 2021)

CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models. - Kensuke Murakami; Mahfuzul Islam 001; Hidetoshi Onodera (IOLTS, 2021)

A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits. - Ryosuke Matsuo; Jun Shiomi; Tohru Ishihara; Hidetoshi Onodera; Akihiko Shinya; Masaya Notomi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation. - Kentaro Nagai; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Electron., 2021)

Supplemental PDK for ASAP7 Using Synopsys Flow. - Shinichi Nishizawa; Shih-Ting Lin; Yih-Lang Li; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2021)

MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching. - Hongjie Xu; Jun Shiomi; Hidetoshi Onodera (IEEE Open J. Circuits Syst., 2021)

Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (LASCAS, 2022)

Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. - Jun Shiomi; Shogo Terada; Tohru Ishihara; Hidetoshi Onodera (SOCC, 2022)

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region. - Shoya Sonoda; Jun Shiomi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)