Base Address Recognition with Data Flow Tracking for Injection Attack Detection. - Satoshi Katsunuma; Hiroyuki Kurita; Ryota Shioya; Kazuto Shimizu; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (PRDC, 2006)

Utilization of SECDED for soft error and variation-induced defect tolerance in caches. - Luong Dinh Hung; Hidetsugu Irie; Masahiro Goshima; Shuichi Sakai (DATE, 2007)

Preventing timing errors on register writes: mechanisms of detections and recoveries. - Hidetsugu Irie; Ken Sugimoto; Masahiro Goshima; Shuichi Sakai (SIGARCH Comput. Archit. News, 2007)

Low-Complexity Bypass Network Using Small RAM. - Shinobu Miwa; Hironori Ichibayashi; Hidetsugu Irie; Masahiro Goshima; Hironori Nakajo; Shinji Tomita (CDES, 2008)

Ultra Dependable Processor. - Shuichi Sakai; Masahiro Goshima; Hidetsugu Irie (IEICE Trans. Electron., 2008)

An Efficient Path Setup for a Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (ICNC, 2010)

CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution. - Takefumi Miyoshi; Kenji Kise; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2010)

Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster. - Qin Wang; Junichi Ohmura; Axida Shan; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2010)

OREX - An Optical Ring with Electrical Crossbar Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Ping Qiu; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (IWIA, 2010)

CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection. - Hidetsugu Irie; Takefumi Miyoshi; Goki Honjo; Kei Hiraki; Tsutomu Yoshinaga (ICNC, 2011)

Multi-GPU Acceleration of Optical Flow Computation in Visual Functional Simulation. - Junichi Ohmura; Akira Egashira; Shunji Satoh; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2011)

Computation-Communication Overlap of Linpack on a GPU-Accelerated PC Cluster. - Junichi Ohmura; Takefumi Miyoshi; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2011)

An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. - Cisse Ahmadou Dit Adi; Hiroki Matsutani; Michihiro Koibuchi; Hidetsugu Irie; Takefumi Miyoshi; Tsutomu Yoshinaga (Int. J. Netw. Comput., 2011)

FLAT: a GPU programming framework to provide embedded MPI. - Takefumi Miyoshi; Hidetsugu Irie; Keigo Shima; Hiroki Honda; Masaaki Kondo; Tsutomu Yoshinaga (GPGPU@ASPLOS, 2012)

Parallel Numerical Simulation of Visual Neurons for Analysis of Optical Illusion. - Akira Egashira; Shunji Satoh; Hidetsugu Irie; Tsutomu Yoshinaga (ICNC, 2012)

STRAIGHT: Realizing a Lightweight Large Instruction Window by Using Eventually Consistent Distributed Registers. - Hidetsugu Irie; Daisuke Fujiwara; Kazuki Majima; Tsutomu Yoshinaga (ICNC, 2012)

Throttling Control for Bufferless Routing in On-chip Networks. - Yicheng Guan; Cisse Ahmadou Dit Adi; Takefumi Miyoshi; Michihiro Koibuchi; Hidetsugu Irie; Tsutomu Yoshinaga (MCSoC, 2012)

Using Cacheline Reuse Characteristics for Prefetcher Throttling. - Hidetsugu Irie; Takefumi Miyoshi; Goki Honjo; Kei Hiraki; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2012)

A real-time gait improvement tool using a smartphone. - Hirotaka Kashihara; Hiroki Shimizu; Hiroyoshi Houchi; Masato Yoshimi; Tsutomu Yoshinaga; Hidetsugu Irie (AH, 2013)

Sharing Computing Resources with Virtual Machines by Transparent Data Access. - Takuma Nakajima; Masato Yoshimi; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2013)

An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2013)

A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. - Cisse Ahmadou Dit Adi; Michihiro Koibuchi; Masato Yoshimi; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2013)

Accelerating OLAP Workload on Interconnected FPGAs with Flash Storage. - Masato Yoshimi; Ryu Kudo; Yasin Oge; Yuta Terada; Hidetsugu Irie; Tsutomu Yoshinaga (CANDAR, 2014)

An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications. - Masato Yoshimi; Ryu Kudo; Yasin Oge; Yuta Terada; Hidetsugu Irie; Tsutomu Yoshinaga (MCSoC, 2014)

Design and Evaluation of a Configurable Query Processing Hardware for Data Streams. - Yasin Oge; Masato Yoshimi; Takefumi Miyoshi; Hideyuki Kawashima; Hidetsugu Irie; Tsutomu Yoshinaga (IEICE Trans. Inf. Syst., 2015)

"Stubborn" strategy to mitigate remaining cache misses. - Hayato Nomura; Hiroyuki Katchi; Hidetsugu Irie; Shuichi Sakai (ICCD, 2016)

High-Accuracy Joint Position Estimation and Posture Detection System for Driving. - Takahiro Yamada; Hidetsugu Irie; Shuichi Sakai (MobiQuitous (Adjunct Proceedings), 2016)

Accelerating Integrity Verification on Secure Processors by Promissory Hash. - Mizuki Miyanaga; Hidetsugu Irie; Shuichi Sakai (PRDC, 2017)

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. - Junichiro Kadomoto; Toru Koizumi 001; Akifumi Fukuda; Reoma Matsuo; Susumu Mashimo; Akifumi Fujita; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPT, 2018)

Reduction of Instruction Increase Overhead by STRAIGHT Compiler. - Toru Koizumi 001; Satoshi Nakae; Akifumi Fukuda; Hidetsugu Irie; Shuichi Sakai (CANDAR Workshops, 2018)

Estimating driver's readiness by understanding driving posture. - Takahiro Yamada; Hidetsugu Irie; Masahiro Kunitake; Eiji Nagano; Shuichi Sakai (ICCE, 2018)

STRAIGHT: Hazardless Processor Architecture Without Register Renaming. - Hidetsugu Irie; Toru Koizumi 001; Akifumi Fukuda; Seiya Akaki; Satoshi Nakae; Yutaro Bessho; Ryota Shioya; Takahiro Notsu; Katsuhiro Yoda; Teruo Ishihara; Shuichi Sakai (MICRO, 2018)

WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2019)

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. - Susumu Mashimo; Koji Inoue; Ryota Shioya; Akifumi Fujita; Reoma Matsuo; Seiya Akaki; Akifumi Fukuda; Toru Koizumi 001; Junichiro Kadomoto; Hidetsugu Irie; Masahiro Goshima (FPT, 2019)

An Inductively Coupled Wireless Bus for Chiplet-Based Systems. - Junichiro Kadomoto; Satoshi Mitsuno; Hidetsugu Irie; Shuichi Sakai (ASP-DAC, 2020)

A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (AsianCHI@CHI, 2020)

A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (COOL CHIPS, 2020)

A High-Performance Out-of-Order Soft Processor Without Register Renaming. - Satoshi Mitsuno; Junichiro Kadomoto; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (FPL, 2020)

Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2020)

Compiling and Optimizing Real-world Programs for STRAIGHT ISA. - Toru Koizumi 001; Shu Sugita; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. - Tomoki Nakamura; Kazutaka Tomida; Shouta Kouno; Hidetsugu Irie; Shuichi Sakai (ICCD, 2021)

Multiport Register File Design for High-Performance Embedded Cores. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MCSoC, 2021)

Toward Wirelessly Cooperated Shape-Changing Computing Particles. - Junichiro Kadomoto; Takuya Sasatani; Koya Narumi; Naoto Usami; Hidetsugu Irie; Shuichi Sakai; Yoshihiro Kawahara (IEEE Pervasive Comput., 2021)

Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (ASP-DAC, 2022)

T-SKID: Predicting When to Prefetch Separately from Address Prediction. - Toru Koizumi 001; Tomoki Nakamura; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (DATE, 2022)

Evaluation of Different Microarchitectures for Energy-Efficient RISC-V Cores. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MCSoC, 2022)

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. - Shu Sugita; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (CC, 2023)

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. - Taichi Amano; Junichiro Kadomoto; Satoshi Mitsuno; Toru Koizumi 001; Ryota Shioya; Hidetsugu Irie; Shuichi Sakai (ISCAS, 2023)

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. - Toru Koizumi 001; Ryota Shioya; Shu Sugita; Taichi Amano; Yuya Degawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (MICRO, 2023)

Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. - Kenta Higuchi; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SenSys, 2023)

Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SenSys, 2023)

A Functional Reactive Programming Language for Wirelessly Connected Shape-Changeable Chiplet-Based Computers. - Yusuke Izawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (SPLASH Companion, 2023)

iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. - Takashi Murayama; Shu Sugita; Hiroyuki Saegusa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (UIST (Adjunct Volume), 2023)

Dynamically Reconfigurable Network Protocol for Shape-Changeable Computer System. - Shun Nagasaki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEEE Des. Test, 2023)

A Principal Factor of Performance in Decoupled Front-End. - Yuya Degawa; Toru Koizumi 001; Tomoki Nakamura; Ryota Shioya; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

FPGA-based Garbling Accelerator with Parallel Pipeline Processing. - Rin Oishi; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEICE Trans. Inf. Syst., 2023)

A Wireless Data and Power Transfer-Enabled MCU for Shape-Configurable Chiplet-Based Computers. - Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (APCCAS, 2024)

A Dynamic Approximation Processor Based on Out-of-Order RISC-V in 28-nm CMOS. - Tomohiro Yoshita; Junichiro Kadomoto; Hidetsugu Irie (APCCAS, 2024)

Designing a Reactive Programming Language for Shape-Adaptive Computers. - Yusuke Izawa; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (APSEC, 2024)

Multi-Tree Network Protocol Enabling System Partitioning for Shape-Changeable Computer System. - Shun Nagasaki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (CF, 2024)

CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. - Masato Goto; Ibuki Sugiyama; Kenta Higuchi; Toshiki Goto; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (CHI Extended Abstracts, 2024)

Branch Divergence-Aware Flexible Approximating Technique on GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (COOL CHIPS, 2024)

A Convenient Approach for Lane-Level Congestion Detection with On-Board Camera Images and Vehicle Data. - Hiroki Taniai; Yusuke Yamaura; Shintaro Fukushima; Junichiro Kadomoto; Hidetsugu Irie (ITSC, 2024)

Preliminary Design Space Exploration for ASIC Implementation of Control Systems in Fault-Tolerant Quantum Computers. - Junichiro Kadomoto; Takuya Kasamura; Hidetsugu Irie (QCE, 2024)

DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication. - Shoi To; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (UIST (Adjunct Volume), 2024)

Cycle-Oriented Dynamic Approximation: Architectural Framework to Meet Performance Requirements. - Yuya Degawa; Shota Suzuki; Junichiro Kadomoto; Hidetsugu Irie; Shuichi Sakai (IEEE Comput. Archit. Lett., 2024)

TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Comput. Archit. Lett., 2024)

Biotite: A High-Performance Static Binary Translator using Source-Level Information. - Changbin Chen; Shu Sugita; Yotaro Nada; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (CC, 2025)

ReconSkin: Shape-Configurable Robotic Skin Utilizing Wireless Networked Sensor Nodes. - Masato Goto; Ibuki Sugiyama; Junichiro Kadomoto; Hidetsugu Irie; Yoshio Mita (CHI Extended Abstracts, 2025)

Enhancing GPU Performance Through Complexity-Effective Out-of-Order Execution Using Distance-Based ISA. - Reoma Matsuo; Toru Koizumi 001; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEICE Trans. Inf. Syst., 2025)

Flexible Approximate Computing for Mitigating Branch Divergence in GPUs. - Reoma Matsuo; Yuya Degawa; Hidetsugu Irie; Shuichi Sakai; Ryota Shioya (IEEE Micro, 2025)