Investigation of multi cell upset in sequential logic and validity of redundancy technique. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Keiji Takahisa; Mitsuhiro Fukuda; Kichiji Hatanaka (IOLTS, 2011)

Critical charge dependence of correlation of different neutron sources for soft error testing. - Hiroko Mori; Taiki Uemura; Hideya Matsuyama; Shin-ichiro Abe; Yukinobu Watanabe (IRPS, 2015)

Impact of package on neutron induced single event upset in 20 nm SRAM. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto (IRPS, 2015)

Soft error immune latch design for 20 nm bulk CMOS. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto (IRPS, 2015)

Verification of Copper Stress Migration Under Low Temperature Long Time Stress. - Hideya Matsuyama; Takashi Suzuki; Motoki Shiozu; Hideo Ehara; Takeshi Soeda; Hirokazu Hosoi; Masao Oshima; Kikuo Yamabe (IRPS, 2019)