A 256-Mb SDRAM using a register-controlled digital DLL. - Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shin-ya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; et al. (IEEE J. Solid State Circuits, 1997)

PLE for automotive braking system with management of impacts from equipment interactions. - Takahiro Iida; Masahiro Matsubara; Kentaro Yoshimura; Hideyuki Kojima; Kimio Nishino (SPLC, 2016)