A capacitorless twin-transistor random access memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (CICC, 2005)

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. - Hideyuki Noda; Katsumi Dosaka; Fukashi Morishita; Kazutami Arimoto (CICC, 2005)

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. - Kazunari Inoue; Hideyuki Noda; Kazutami Arimoto; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Trans. Electron., 2005)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS. - Isamu Hayashi; Teruhiko Amano; Naoya Watanabe; Yuji Yano; Yasuto Kuroda; M. Shirata; Katsumi Dosaka; Koji Nii; Hideyuki Noda; Hiroyuki Kawai (IEEE J. Solid State Circuits, 2013)

Low-power multi-sensor system with normally-off sensing technology for IoT applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Hiroyuki Kondo (ISOCC, 2016)

Low-power multi-sensor system with task scheduling and autonomous standby mode transition control for IoT applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Koji Nii; Hiroyuki Kondo (COOL Chips, 2017)

3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. - Hayato Kimura 003; Hideyuki Noda; Hisaaki Watanabe; Takashi Higuchi; Ryosaku Kobayashi; Masayuki Utsuno; Fumitake Takami; Sugako Otani; Masayuki Ito; Yasuhisa Shimazaki; Naoki Yada; Hiroyuki Kondo (ISSCC, 2017)

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT Applications. - Masanori Hayashikoshi; Hideyuki Noda; Hiroyuki Kawai; Yasumitsu Murai; Sugako Otani; Koji Nii; Yoshio Matsuda; Hiroyuki Kondo (IEEE Trans. Multi Scale Comput. Syst., 2018)

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT Applications. - Masanori Hayashikoshi; Hiroaki Tanizaki; Yasumitsu Murai; Takaharu Tsuji; Kiyoshi Kawabata; Koji Nii; Hideyuki Noda; Hiroyuki Kondo; Yoshio Matsuda; Hideto Hidaka (IEICE Trans. Electron., 2019)