A direct digital synthesizer with interpolation circuits. - Tadao Nakagawa; Hideyuki Nosaka (IEEE J. Solid State Circuits, 1997)

Authors' Reply. - Tadao Nakagawa; Hideyuki Nosaka (IEEE J. Solid State Circuits, 1998)

A low-power direct digital synthesizer using a self-adjusting phase-interpolation technique. - Hideyuki Nosaka; Yo Yamaguchi; Akihiro Yamagishi; Hiroyuki Fukuyama; Masahiro Muraguchi (IEEE J. Solid State Circuits, 2001)

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistors. - Kiyoshi Ishii; Hideyuki Nosaka; Hiroki Nakajima; Kenji Kurishima; Minoru Ida; Noriyuki Watanabe; Yasurou Yamane; Eiichi Sano; Takatomo Enoki (IEEE J. Solid State Circuits, 2002)

A Fractional Phase Interpolator Using Two-Step Integration for Frequency Multiplication and Direct Digital Synthesis. - Hideyuki Nosaka; Yo Yamaguchi; Akihiro Yamagishi; Masahiro Muraguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator. - Hideyuki Nosaka; Kiyoshi Ishii; Takatomo Enoki; Tsugumichi Shibata (IEEE J. Solid State Circuits, 2003)

High-bit-rate low-power decision circuit using InP/InGaAs HBT technology [master-slave D-type flip-flop]. - Kiyoshi Ishii; Hideyuki Nosaka; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Takatorno Enoki; Tsugumichi Shibata (ESSCIRC, 2004)

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. - Hideyuki Nosaka; Eiichi Sano; Kiyoshi Ishii; Minoru Ida; Kenji Kurishima; Shoji Yamahata; Tsugumichi Shibata; Hiroyuki Fukuyama; Mikio Yoneyama; Takatomo Enoki; Masahiro Muraguchi (IEEE J. Solid State Circuits, 2004)

A 24-Gsps 3-Bit Nyquist ADC Using InP HBTs for DSP-Based Electronic Dispersion Compensation. - Hideyuki Nosaka; Makoto Nakamura; Kimikazu Sano; Minoru Ida; Kenji Kurishima; Tsugumichi Shibata; Masami Tokumitsu; Masahiro Muraguchi (IEICE Trans. Electron., 2005)

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology. - Kiyoshi Ishii; Hideyuki Nosaka; Kimikazu Sano; Koichi Murata; Minoru Ida; Kenji Kurishima; Michihiro Hirata; Tsugumichi Shibata; Takatomo Enoki (IEEE J. Solid State Circuits, 2005)

A 24-GS/s 6-bit R-2R Current-Steering DAC in InP HBT Technology. - Munehiko Nagatani; Hideyuki Nosaka; Shogo Yamanaka; Kimikazu Sano; Koichi Murata (IEICE Trans. Electron., 2010)

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems. - Munehiko Nagatani; Hideyuki Nosaka; Shogo Yamanaka; Kimikazu Sano; Koichi Murata (IEEE J. Solid State Circuits, 2011)

Wide dynamic range transimpedance amplifier IC for 100-G DP-QPSK optical links using 1-µm InP HBTs. - Kimikazu Sano; Hiroyuki Fukuyama; Makoto Nakamura; Miwa Mutoh; Hideyuki Nosaka; Koichi Murata (IEICE Electron. Express, 2012)

A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. - Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka; Akira Tsuchiya; Hidetoshi Onodera; Shunji Kimura (A-SSCC, 2015)

160-Gbps Nyquist PAM4 transmitter using a digital-preprocessed analog-multiplexed DAC. - Hiroshi Yamazaki; Munehiko Nagatani; Shigeru Kanazawa; Hideyuki Nosaka; Toshikazu Hashimoto; Akihide Sano; Yutaka Miyamoto (ECOC, 2015)

5 × 1-Tb/s PDM-16QAM transmission over 1, 920 km using high-speed InP MUX-DAC integrated module. - Akihide Sano; Munehiko Nagatani; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2015)

28 Gbaud 16-QAM modulation with compact driver module for InP MZM. - Hitoshi Wakita; Munehiko Nagatani; Shigeru Kanazawa; Toshihiro Itoh; Eiichi Yamada; Hiroyuki Ishii; Hideyuki Nosaka (IEICE Electron. Express, 2015)

F4: Emerging short-reach and high-density interconnect solutions for internet of everything. - Ichiro Fujimori; Martin Brox; Elad Alon; Pavan Kumar Hanumolu; Gerrit den Besten; Hideyuki Nosaka (ISSCC, 2016)

High-performance compound-semiconductor integrated circuits for advanced digital coherent optical communications systems. - Munehiko Nagatani; Hideyuki Nosaka (IEICE Electron. Express, 2016)

An InP-Based 27-GHz-Bandwidth Limiting TIA IC Designed to Suppress Undershoot and Ringing in Its Output Waveform. - Hiroyuki Fukuyama; Michihiro Hirata; Kenji Kurishima; Minoru Ida; Masami Tokumitsu; Shogo Yamanaka; Munehiko Nagatani; Toshihiro Itoh; Kimikazu Sano; Hideyuki Nosaka; Koichi Murata (IEICE Trans. Electron., 2016)

A 180-mW Linear MZM Driver in CMOS for Single-Carrier 400-Gb/s Coherent Optical Transmitter. - Shinsuke Nakano; Munehiko Nagatani; Kenji Tanaka; Yoshihiro Ogiso; Josuke Ozaki; Hiroshi Yamazaki; Hideyuki Nosaka (ECOC, 2017)

Ultra-Wideband Digital-to-Analog Conversion Technologies for Tbit/s channel transmission. - Hiroshi Yamazaki; Munehiko Nagatani; Fukutaro Hamaoka; Shigeru Kanazawa; Hideyuki Nosaka; Toshikazu Hashimoto; Yutaka Miyamoto (ECOC, 2017)

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. - Tomonori Tanaka; Kosuke Furuichi; Hiromu Uemura; Ryosuke Noguchi; Natsuyuki Koda; Koki Arauchi; Daichi Omoto; Hiromi Inaba; Keiji Kishine; Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka (ISCAS, 2017)

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. - Yohan Frans; Ichiro Fujimori; Seung-Jun Bae; Samuel Palermo; Hideyuki Nosaka; Simone Erba (ISSCC, 2017)

Session 29 overview: Optical- and electrical-link innovations. - Samuel Palermo; Hideyuki Nosaka; Frank O'Mahony (ISSCC, 2017)

A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. - Akitaka Hiratsuka; Akira Tsuchiya; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (A-SSCC, 2018)

A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8× Time-Domain Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (A-SSCC, 2018)

A 256-Gbps PAM-4 Signal Generator IC in 0.25-µm InP DHBT Technology. - Munehiko Nagatani; Hitoshi Wakita; Teruo Jyo; Miwa Mutoh; Minoru Ida; Sorin P. Voinigescu; Hideyuki Nosaka (BCICTS, 2018)

Transmission of 400-Gbps Discrete Multi-Tone Signal Using >100-GHz-Bandwidth Analog Multiplexer and InP Mach-Zehnder Modulator. - Hiroshi Yamazaki; Munehiko Nagatani; Hitoshi Wakita; Yoshihiro Ogiso; Masanori Nakamura; Minoru Ida; Toshikazu Hashimoto; Hideyuki Nosaka; Yutaka Miyamoto (ECOC, 2018)

A 137-mW, 4 ch × 25-Gbps Low-Power Compact Transmitter Flip-Chip-Bonded 1.3-μm LD-Array-on-Si. - Toshiki Kishi; Munehiko Nagatani; Shigeru Kanazawa; Shinsuke Nakano; Hiroaki Katsurai; Takuro Fujii; Hidetaka Nishi; Takaaki Kakitsuka; Koichi Hasebe; Kota Shikama; Yuko Kawajiri; Atsushi Aratake; et al. (OFC, 2018)

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. - Ryosuke Noguchi; Kosuke Furuichi; Hiromu Uemura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Hiroaki Katsurai; Shinsuke Nakano; Hideyuki Nosaka (VLSI-DAT, 2018)

A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

300-GHz 120-Gb/s Wireless Transceiver with High-Output-Power and High-Gain Power Amplifier Based on 80-nm InP-HEMT Technology. - Hiroshi Hamada; Takuya Tsutsumi; Go Itami; Hiroki Sugiyama; Hideaki Matsuzaki; Kenichi Okada 001; Hideyuki Nosaka (BCICTS, 2019)

A 110-GHz-Bandwidth 2: 1 AMUX-Driver using 250-nm InP DHBTs for Beyond-1-Tb/s/carrier Optical Transmission Systems. - Munehiko Nagatani; Yutaka Miyamoto; Hideyuki Nosaka; Hitoshi Wakita; Yoshihiro Ogiso; Hiroshi Yamazaki; Miwa Mutoh; Minoru Ida; Fukutaro Hamaoka; Masanori Nakamura; Takayuki Kobayashi (BCICTS, 2019)

120-GBaud 32QAM Signal Generation using Ultra-Broadband Electrical Bandwidth Doubler. - Fukutaro Hamaoka; Masanori Nakamura; Munehiko Nagatani; Takayuki Kobayashi; Asuka Matsushita; Hitoshi Wakita; Hiroshi Yamazaki; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2019)

A 25-Gbps × 4 ch, Low-Power Compact Wire-Bond-Free 3D-Stacked Transmitter Module with 1.3-μm LD-Array-on-Si for On-Board Optics. - Toshiki Kishi; Hitoshi Wakita; Kota Shikama; Munehiko Nagatani; Shigeru Kanazawa; Takuro Fujii; Hidetaka Nishi; Hiroshi Ishikawa; Yuko Kawajiri; Atsushi Aratake; Hideyuki Nosaka; Hiroshi Fukuda; et al. (OFC, 2019)

35-Tb/s C-Band Transmission Over 800 km Employing 1-Tb/s PS-64QAM Signals Enhanced by Complex 8 × 2 MIMO Equalizer. - Takayuki Kobayashi; Masanori Nakamura; Fukutaro Hamaoka; Munehiko Nagatani; Hitoshi Wakita; Hiroshi Yamazaki; Takeshi Umeki; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2019)

192-Gbaud Signal Generation using Ultra-Broadband Optical Frontend Module Integrated with Bandwidth Multiplexing Function. - Masanori Nakamura; Fukutaro Hamaoka; Munehiko Nagatani; Yoshihiro Ogiso; Hitoshi Wakita; Hiroshi Yamazaki; Takayuki Kobayashi; Minoru Ida; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2019)

1.04 Tbps/Carrier Probabilistically Shaped PDM-64QAM WDM Transmission Over 240 km Based on Electrical Spectrum Synthesis. - Masanori Nakamura; Fukutaro Hamaoka; Munehiko Nagatani; Hiroshi Yamazaki; Takayuki Kobayashi; Asuka Matsushita; Seiji Okamoto; Hitoshi Wakita; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2019)

Digital-Preprocessed Analog-Multiplexed DAC for High-Speed Optical Communications. - Hiroshi Yamazaki; Munehiko Nagatani; Hitoshi Wakita; Masanori Nakamura; Fukutaro Hamaoka; Takayuki Kobayashi; Yoshihiro Ogiso; Minoru Ida; Toshikazu Hashimoto; Hideyuki Nosaka; Yutaka Miyamoto (OECC/PSC, 2019)

A 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (SoCC, 2019)

A wideband current-reuse-RGC TIA circuit with low-power consumption. - Akira Hida; Yusuke Nakane; Shunta Mizuno; Makoto Nakamura; Daisuke Ito; Shinsuke Nakano; Hideyuki Nosaka (IEICE Electron. Express, 2019)

230-305 GHz, > 10-dBm-Output-Power Wideband Power Amplifier Using Low-Q Neutralization Technique in 60-nm InP-HEMT Technology. - Hiroshi Hamada; Takuya Tsutsumi; Adam Pander; Masahito Nakamura; Go Itami; Hideaki Matsuzaki; Hiroki Sugiyama; Hideyuki Nosaka (BCICTS, 2020)

An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT. - Teruo Jyo; Munehiko Nagatani; Minoru Ida; Miwa Mutoh; Hitoshi Wakita; Naoki Terao; Hideyuki Nosaka (BCICTS, 2020)

Ultra-wideband Optical Receiver Using Electrical Spectrum Decomposition Technique. - Fukutaro Hamaoka; Masahito Nakamura; Munehiko Nagatani; Hitoshi Wakita; Takayuki Kobayashi; Hiroshi Yamazaki; Hideyuki Nosaka; Yutaka Miyamoto (ECOC, 2020)

12.3 A 48GHz BW 225mW/ch Linear Driver IC with Stacked Current-Reuse Architecture in 65nm CMOS for Beyond-400Gb/s Coherent Optical Transmitters. - Teruo Jyo; Munehiko Nagatani; Josuke Ozaki; Mitsuteru Ishikawa; Hideyuki Nosaka (ISSCC, 2020)

Net 321.24-Gb/s IMDD Transmission Based on a >100-GHz Bandwidth Directly-Modulated Laser. - Nikolaos-Panteleimon Diamantopoulos; Hiroshi Yamazaki; Suguru Yamaoka; Munehiko Nagatani; Hidetaka Nishi; Hiromasa Tanobe; Ryo Nakao; Takuro Fujii; Koji Takeda; Takaaki Kakitsuka; Hitoshi Wakita; Minoru Ida; et al. (OFC, 2020)

A 0.57-mW/Gbps, 2ch × 53-Gbps Low-Power PAM4 Transmitter Front-End Flip-Chip-Bonded 1.3-µm LD-Array-on-Si. - Toshiki Kishi; Munehiko Nagatani; Shigeru Kanazawa; Kota Shikama; Takuro Fujii; Hidetaka Nishi; Hiroshi Yamazaki; Norio Sato; Hideyuki Nosaka; Shinji Matsuo (OFC, 2020)

Long-Haul WDM Transmission with Over-1-Tb/s Channels using Electrically Synthesized High-Symbol-Rate Signals. - Takayuki Kobayashi; Masanori Nakamura; Fukutaro Hamaoka; Munehiko Nagatani; Hiroshi Yamazaki; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2020)

Wideband Inline-Amplified WDM Transmission using PPLN-Based OPA with Over-10-THz Bandwidth. - Takayuki Kobayashi; Shimpei Shimizu; Masahito Nakamura; Takeshi Umeki; Takushi Kazama; Ryoichi Kasahara; Fukutaro Hamaoka; Munehiko Nagatani; Hiroshi Yamazaki; Takayuki Mizuno; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2020)

Entropy and Symbol-Rate Optimized 120 GBaud PS-36QAM Signal Transmission over 2400 km at Net-Rate of 800 Gbps/λ. - Masanori Nakamura; Takayuki Kobayashi; Hiroshi Yamazaki; Fukutaro Hamaoka; Munehiko Nagatani; Hitoshi Wakita; Hideyuki Nosaka; Yutaka Miyamoto (OFC, 2020)

Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS. - Akira Tsuchiya; Akitaka Hiratsuka; Kenji Tanaka; Hiroyuki Fukuyama; Naoki Miura; Hideyuki Nosaka; Hidetoshi Onodera (IEICE Trans. Electron., 2020)

300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers. - Hiroshi Hamada; Takuya Tsutsumi; Hideaki Matsuzaki; Takuya Fujimura; Ibrahim Abdo; Atsushi Shirane; Kenichi Okada 001; Go Itami; Ho-Jin Song; Hiroki Sugiyama; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2020)

A Beyond-1-Tb/s Coherent Optical Transmitter Front-End Based on 110-GHz-Bandwidth 2: 1 Analog Multiplexer in 250-nm InP DHBT. - Munehiko Nagatani; Hitoshi Wakita; Hiroshi Yamazaki; Yoshihiro Ogiso; Miwa Mutoh; Minoru Ida; Fukutaro Hamaoka; Masanori Nakamura; Takayuki Kobayashi; Yutaka Miyamoto; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2020)

22.2 A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Jian Pang; Hiroshi Hamada; Hideyuki Nosaka; Atsushi Shirane; et al. (ISSCC, 2021)

64QAM wireless link with 300GHz InP-CMOS hybrid transceiver. - Ibrahim Abdo; Hiroshi Hamada; Hideyuki Nosaka; Atsushi Shirane; Kenichi Okada 001 (IEICE Electron. Express, 2021)

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8× Time-Domain Latch Interpolation. - Il-Min Yi; Naoki Miura; Hiroyuki Fukuyama; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS. - Il-Min Yi; Naoki Miura; Hideyuki Nosaka (IEEE J. Solid State Circuits, 2021)

A Bi-Directional 300-GHz-Band Phased-Array Transceiver in 65-nm CMOS With Outphasing Transmitting Mode and LO Emission Cancellation. - Ibrahim Abdo; Carrel da Gomez; Chun Wang; Kota Hatano; Qi Li; Chenxin Liu; Kiyoshi Yanagisawa; Ashbir Aviat Fadila; Takuya Fujimura; Tsuyoshi Miura; Korkut Kaan Tokgoz; Jian Pang; et al. (IEEE J. Solid State Circuits, 2022)

A ROM-Less DDS with Single Current-Switch Array Using Self-Adjusting Two-Step Integrator. - Haruki Shibue; Hideyuki Nosaka (RWS, 2023)

17.4 Environmentally-Friendly Disposable Circuit and Battery System for Reducing Impact of E-Wastes. - Naoki Miura; Hiroaki Taguchi; Kazuyoshi Watanabe; Masaya Nohara; Tatsuyuki Makita; Masahiro Tanabe; Takahiro Wakimoto; Shohei Kumagai; Hideyuki Nosaka; Atsushi Aratake; Toshihiro Okamoto; Shun Watanabe; et al. (ISSCC, 2024)

DDS-based Multiphase Local Oscillator Generator for Fast-Beam-Switching Phased-Array Antennas. - Shuichi Inaguma; Koki Nagata; Hideyuki Nosaka (RWS, 2024)