High speed and low power on-chip micro network circuit with differential transmission line. - Shinichiro Gomi; Kohichi Nakamura; Hiroyuki Ito; Hideyuki Sugita; Kenichi Okada 001; Kazuya Masu (SoC, 2004)

Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. - Hiroyuki Ito; Hideyuki Sugita; Kenichi Okada; Tatsuya Ito; Kazuhisa Itoi; Masakazu Sato; Ryozo Yamauchi; Kazuya Masu (IEICE Trans. Electron., 2007)

An 18Gb/s duobinary receiver with a CDR-assisted DFE. - Kazuhisa Sunaga; Hideyuki Sugita; Koichi Yamaguchi; Kazumasa Suzuki (ISSCC, 2009)

A 6Gb/s receiver with discrete-time based channel filtering for wireline FDM communications. - Tsutomu Takeya; Kazuhisa Sunaga; Koichi Yamaguchi; Hideyuki Sugita; Yoichi Yoshida; Masayuki Mizuno; Tadahiro Kuroda (CICC, 2010)

A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS. - Hideyuki Sugita; Kazuhisa Sunaga; Koichi Yamaguchi; Masayuki Mizuno (ISSCC, 2010)