A Hardware Prefetching Mechanism for Vector Gather Instructions. - Hikaru Takayashiki; Masayuki Sato 001; Kazuhiko Komatsu; Hiroaki Kobayashi (IA3@SC, 2019)

An Energy-aware Dynamic Data Allocation Mechanism for Many-channel Memory Systems. - Masayuki Sato 001; Takuya Toyoshima; Hikaru Takayashiki; Ryusuke Egawa; Hiroaki Kobayashi (Supercomput. Front. Innov., 2019)

A Skewed Multi-banked Cache for Many-core Vector Processors. - Hikaru Takayashiki; Masayuki Sato 001; Kazuhiko Komatsu; Hiroaki Kobayashi (Supercomput. Front. Innov., 2019)

Register Flush-free Runahead Execution for Modern Vector Processors. - Hikaru Takayashiki; Masayuki Sato 001; Kazuhiko Komatsu; Hiroaki Kobayashi (SBAC-PAD, 2021)

Page-Address Coalescing of Vector Gather Instructions for Efficient Address Translation. - Hikaru Takayashiki; Masayuki Sato 001; Kazuhiko Komatsu; Hiroaki Kobayashi (IA3@SC, 2022)

A Metadata Prefetching Mechanism for Hybrid Memory Architectures. - Shunsuke Tsukada; Hikaru Takayashiki; Masayuki Sato 001; Kazuhiko Komatsu; Hiroaki Kobayashi (IEICE Trans. Electron., 2022)

A New Sparse GEneral Matrix-matrix Multiplication Method for Long Vector Architecture by Hierarchical Row Merging. - Hikaru Takayashiki; Hotaka Yagi; Hiroki Nishimoto; Naoki Yoshifuji (SC Workshops, 2023)

Performance Analysis of the NICAM Benchmark on MN-Core Processor. - Hikaru Takayashiki; Natsuko Saito; Hiroto Imachi; Ryo Sakamoto; Junichiro Makino (SC Workshops, 2024)